Agilent Technologies, Inc.

Hewlett-packard Company

Ford Motor Company Limited

Verigy Ipco

Kenneth Paul Parker

Chris R Jacobsen

Kenneth E Posse

Myron J Schneider

John E McDermid

Ronald J Peiffer

Jacob Lee Bell

Glen E Leinbach

Kathleen J Hird

Erik A Ramos

Young Gon Kim

Jeff Rearick

Benny W H Lai

Nurwati Suwendi Devnani

Myunghee Lee

David J Rustici

Dayton Norrgard

Stig Oresjo

Tak Yee Kwan

Robert Mayrus Tromp

Heather M Ryan

John E Herczeg

Richard W Rivas, Sr

Hiroyuki Ohki

Muneo Kawabata

Keisuke Takaura

Daniel G Bihn

James L Hutchinson

Joseph M Lagrotta

Takanori Uematsu

Stig Herman Oresjo

Carl Wilmer Thatcher

One or more test probe access structures for accessing vias on a printed circuit assembly and method of fabrication thereof is presented. Each test probe access structure is conductively connected to a via at a test probe access location above an exposed surface of a via to be accessible for probing by a test probe.

Method and apparatus for manufacturing and probing test probe access structures on vias

A test access point structure for accessing test points of a printed circuit board and method of fabrication thereof is presented. Each test access point structure is conductively connected to a trace at a test access point and above an exposed surface of the printed circuit board to be accessible for probing by a fixture probe. The test access point structure may be designed and manufactured to permit deformation of the test access point structure upon initial probing of the test access point structure with a fixture probe to ensure electrical contact between the fixture probe and the test access point structure.

Method and apparatus for manufacturing and probing printed circuit board test access point structures

Disclosed herein are various methods and apparatus related to Boundary-Scan testing, including a method for generating Boundary-Scan test vectors. The method assigns different binary signatures to all of the drivers and hysteretic test receiver memories of a circuit assembly under test, and then generates a series of Boundary-Scan test vectors wherein each test vector is derived from corresponding bits of the binary signatures.

Boundary-Scan methods and apparatus

A method and apparatus for detecting open defects on non-probed node under test of an electrical device using capacitive lead frame technology is presented. In accordance with the method of the invention, a probed node neighboring the non-probed node under test is stimulated with a known source signal. A sensor of a capacitive sensing probe is capacitively coupled to at least the probed node and non-probed node under test of the electrical device, and a measuring device coupled to the capacitive sensing probe measures a capacitively coupled signal present between the sensor of the probe and at least the probed and non-probed node of the electrical device. Based on the value of the capacitively sensed signal, a known expected 'defect-free' capacitively sensed signal measurement and/or a known expected 'open' capacitively sensed signal measurement, a determination is made of whether an open defect exists on the non-probed node under test of the electrical device.

Methods and apparatus for non-contact testing and diagnosing of open connections on non-probed nodes

Techniques for automating probing location selection during printed circuit board (PCB) and corresponding PCB tester fixture design are presented. The invention includes a system and algorithm for selecting a probe layout comprising a set of probing locations for a printed circuit board design having a plurality of nets, at least some of which have a number of alternative possible probing locations. The system and algorithm iteratively generates a potential probe layout comprising one or more probing locations per net, and based on the potential probe layout, determines one or more regions of maximum deflection. A probing location from the potential probe layout that is located in a region of maximum deflection and is associated with a net having one or more alternative probing locations is removed from the potential probe layout and replaced in the with one of the one or more alternate probing locations associated with the net. Regions of maximum deflection are recalculated based on the modified potential probe layout, and the replacement process is repeated until respective magnitudes of the respective areas of maximum deflection are below a threshold value.

Method and apparatus for determining probing locations for a printed circuit board

A method and apparatus is presented for gaining socket testability through the use of a capacitive interposer engineered to create capacitive coupling between signal nodes of a circuit assembly that the tester has access to and nodes of the socket that would not otherwise have any coupling to a testable signal node of the socket. Generally, coupling capacitance is engineered into the interposer by trace and via routing between the signal node of the socket and a location in close proximity to the inaccessible socket node such that their proximity to each other couples them together.

Method and apparatus for engineering a testability interposer for testing sockets and connectors on printed circuit boards

A method and apparatus for detecting open defects on grounded nodes of an electrical device using capacitive lead frame technology is presented. In accordance with the method of the invention, an accessible signal node that is capacitively coupled the grounded node is stimulated with a known source signal. A capacitive sense plate is capacitively coupled to the stimulated node and grounded node of the electrical device, and a measuring device coupled to the capacitive sense plate capacitively senses a resulting signal. The value of the capacitively sensed signal is indicative of the presence or non-presence of an open defect on one or both of the grounded node and stimulated signal node.

Methods and apparatus for unpowered testing of open connections on power and ground nodes of circuit devices

A test access point structure for accessing test points of a printed circuit board and method of fabrication thereof is presented. In an x-, y-, z-coordinate system where traces are printed along an x-y plane, the z-dimension is used to implement test access point structures. Each test access point structure is conductively connected to a trace at a test access point directly on top of the trace and along the z axis of the x-, y-, z-coordinate system above an exposed surface of the printed circuit board to be accessible for electrical probing by an external device.

Printed circuit board test access point structures and method for making the same

Non-contact connectivity testing of joints connecting circuit junctions are improved through knowledge of characteristics of semiconductor junctions connected to component nodes of components of a device under test (DUT) to allow detection of high-impedance joints.

Method for non-contact testing of marginal integrated circuit connections

A twisting fixture probe for cleaning oxides, residues or other contaminants from the surface of a solder bead probe and probing a solder bead probe on a printed circuit board during in-circuit testing.

Method and apparatus for a twisting fixture probe for probing test access point structures

A method and apparatus for detecting shorts between accessible and inaccessible signal nodes (e.g., integrated circuit pins) of an electrical device (e.g., an integrated circuit), using capacitive lead frame technology is presented. In accordance with the method of the invention, an accessible node under test is stimulated with a known source signal. A capacitive sense plate is capacitively coupled to at least one of the accessible node and inaccessible node of the electrical device, and a measuring device coupled to the capacitive sense plate capacitively senses a signal present on the at least one of the accessible node and inaccessible node of the electrical device. Based on the value of the capacitively sensed signal, a known expected 'defect-free' capacitively sensed signal measurement and/or a known expected 'shorted' capacitively sensed signal measurement, one can determine whether a short fault exists between the accessible node and inaccessible node of the electrical device.

Methods and apparatus for non-contact testing and diagnosing of inaccessible shorted connections

A method for testing for a defect condition on a node-under-implicit-test of an electrical device is presented. The technique according to the invention includes stimulating a first node of the electrical device that is capacitively coupled to the node-under-implicit-test with a known source signal, and capacitively sensing a signal on a second node of the electrical device that is capacitively coupled to the node-under-implicit-test. A defect condition such as a short or open can be determined from the capacitively sensed signal.

Method for non-contact testing of fixed and inaccessible connections without using a sensor plate

A layout independent test access point structure for accessing test points of a printed circuit board and method of fabrication thereof is presented. Each test access point structure is conductively connected to various locations along a trace at a test access point and above an exposed surface of the printed circuit board to be accessible for probing by a fixture probe.

Method and apparatus for layout independent test point placement on a printed circuit board

Techniques for automating test pad insertion in a printed circuit board (PCB) design and fixture probe insertion in a PCB tester fixture are presented. A probe location algorithm predictably determines respective preferred probing locations from among respective sets of potential probing locations associated with a number of respective nets in a PCB design. Test pads, preferably in the form of bead probes, are added to the PCB design at the respective preferred probing locations along with, where feasible, one or more alternate probing locations chosen from among remaining ones of the respective sets of potential probing locations. During fixture design, nets with multiple test pads implemented in the PCB design are processed by the same probe location algorithm used during PCB design to determine the associated preferred and alternate probing locations for said respective nets. Fixture probes are preferably inserted in the PCB tester fixture design at respective preferred probing locations such that tips of said respective fixture probes exactly align with corresponding preferred test pads of a PCB implemented in accordance with the PCB design should the PCB be mounted in a printed circuit board tester fixture implemented in accordance with the PCB tester fixture design.

Method and system for implicitly encoding preferred probing locations in a printed circuit board design for use in tester fixture build

In one embodiment, a method for testing continuity of electrical paths through a circuit assembly includes: 1) mating a test-facilitating circuit package to a connector of the circuit assembly; the circuit package having a plurality of contacts for mating to a plurality of contacts of the connector; the circuit package containing incomplete or no mission circuitry for the circuit assembly, but containing a plurality of passive circuit components coupled in parallel between the package's plurality of contacts and a test sensor port of the circuit package; 2) stimulating one or more nodes of the circuit assembly; 3) measuring an electrical characteristic of the circuit package; and 4) comparing the measured electrical characteristic to at least one threshold to assess continuities of at least two electrical paths through the circuit assembly. Other embodiments are also disclosed.

Growing community of inventors

Fort Collins, CO, United States of America

Kenneth Paul Parker