Fairchild Semiconductor Corporation

Agere Systems Inc.

National Semiconductor Corporation

Fairchild Semiconductor Corporaton

Kenneth Patrick Snowdon

Nickole Gagne

Roy L Yarbrough

Julie Lynn Stultz

James A Siulinski

Lei Huang

Hrvoje Jasa

Gary D Polhemus

Taeghyun Kang

Na Meng

James Hall

Yongliang Li

Tyler Daigle

Robert A Card

Ivan Duzevik

John R Turner

William Robert Newberry

Christopher A Bennett

John E Scoggins

Kenneth O'Brien

Bert Marston

Michael Smith

Nathan Charland

Alister Young

Randall Wetzel

Jeffrey S Martin

A switch device includes a common node that is connected to end nodes, such as that of computer interface ports. The switch device includes several switch circuits that can be connected in series to form a switch path between the common node and an end node. A switch circuit can include a main switch, such as a transistor that can be configured to withstand a positive or negative voltage surge by automatically changing the connection of its gate.

Switch device with switch circuits that provide high voltage surge protection

This document discusses, among other things, an electronic circuit and method for defaulting to a valid battery supply to power an electronic device. In an example, an electronic circuit can be configured to receive information about the battery supply (e.g., an internal battery), such as the battery supply voltage (V), and to determine if the battery supply is valid or invalid using the received information (e.g., comparing the Vto a threshold). If Vis valid, the electronic device can default to receiving power from the battery supply. If Vis invalid, the electronic device can receive power from another power supply, such as an external supply.

Vpower switch

A switch device includes a common node that is connected to end nodes, such as that of computer interface ports. The switch device includes several switch circuits that can be connected in series to form a switch path between the common node and an end node. A switch circuit can include a main switch, such as a transistor that can be configured to withstand a positive or negative voltage surge by automatically changing the connection of its bulk.

In a general aspect, a circuit can include a first resistor configured to be coupled to a first terminal of a temperature-sensitive resistance, a second resistor configured to be coupled to a second terminal of the temperature-sensitive resistance and a temperature information circuit. The temperature information circuit can be configured to: receive a first voltage from the first terminal of the temperature-sensitive resistance; receive a second voltage from the second terminal of the temperature-sensitive resistance; and provide temperature information based on the first voltage and the second voltage. The temperature information circuit can include a first comparison circuit configured to determine a difference between the first voltage and the second voltage, and a second comparison circuit configured to compare an output of the first comparison circuit to a reference.

Differential thermistor circuit

Systems and methods are disclosed, including, for example, a low-voltage control circuit configured to receive a charge pump voltage, a rail voltage, and a switch control signal, to provide the charge pump voltage when the switch control signal is in a first state, and to provide the higher of the charge pump voltage and the rail voltage when the switch control signal is in a second state. The system can include a first pick-high circuit configured to receive the rail voltage and the charge pump voltage, and to provide the higher of the rail voltage and the charge pump voltage at an output. The switch control signal, in the first state, can include the output of the pick-high circuit. Methods of forming such apparatus are disclosed, as well as methods of operation, and other embodiments.

Low voltage switch control

This document discusses, among other things, an auxiliary self-protecting transistor circuit, system, and method configured to protect a complementary metal-oxide semiconductor (CMOS) transistor. The auxiliary self-protecting transistor circuit can include an ESD device including a gate terminal, a drain terminal, and a source terminal. The ESD device is configured to be coupled to an isolation region of a complementary metal-oxide semiconductor (CMOS) transistor, and can provide a discharge path between the isolation region of the CMOS transistor and the source terminal of the ESD device. The isolation region of the CMOS transistor can include a blocking junction, such as an n-doped isolation well (niso), a p-type well (pwell), or one or more other blocking junctions.

Auxiliary self-protecting transistor structure

Systems and methods are disclosed, including a protection multiplexer circuit configured to receive a control signal and a reference voltage, to provide the reference voltage at an output when the control signal is in a first state, and to isolate the reference voltage from the output when the control signal is in a second state. The protection multiplexer circuit includes cascaded first and second transistors, wherein the first transistor is a native transistor. Control inputs of the first and second transistors are configured to receive the control signal, a first terminal of the first transistor is configured to receive the reference voltage, and the first terminal of the second transistor is coupled to the output. Methods of operation are disclosed, and other embodiments.

Enhanced protective multiplexer

This document discusses, among other things, a biased electrostatic discharge (ESD) circuit and method configured to reduce capacitance of an ESD structure with little to no change in other ESD structure parameters. A bulk terminal of an ESD device can be negative biased to reduce a drain terminal to source terminal capacitance of the ESD device. A charge pump can be configured to provide a negative bias to the bulk terminal of the ESD device. In certain examples, the gate terminal of the ESD device can be coupled to the source terminal of the ESD device, such as through a resistor, and the source terminal can be coupled to ground.

Biased ESD circuit

This document discusses, among other things, an apparatus and method for providing temperature information. In an example, an integrated circuit apparatus can include a first resistor configured to be coupled to a first terminal of a temperature-sensitive resistance, a second resistor configured to be coupled to a second terminal of the temperature-sensitive resistance, and a temperature information circuit configured to receive a first voltage from the first terminal of the temperature-sensitive resistance and a second voltage from the second terminal of the temperature-sensitive resistance. The temperature information circuit can provide the temperature information using the first and second voltages.

An apparatus comprises a connector configured to receive an electrical contact of an accessory device that is electrically coupled to a resistor of the accessory device, a current source configured to apply a specified current to the resistor to generate a resulting voltage, a comparator configured to receive and compare the resulting voltage to a reference voltage, and a controller configured to store an outcome of the comparison as a bit in a register, to adjust the applied current using the outcome of the comparison, and to determine a resistance value for the resistor using the bit stored in the register.

Successive approximation resistor detection

Fuse driver circuits, fuse driver testing circuitry, and methods for testing the fuse driver circuits using the testing circuitry are described. In some embodiments, the fuse driver circuit can be made using a fuse, a NMOS transistor, and a PMOS transistor. The drain of the NMOS transistor can be connected to the negative end of the fuse. The source of the NMOS transistor can be connected to ground. The drain of the PMOS transistor can be connected to a positive end of the fuse. The NMOS and PMOS transistors provide enhanced robustness to the fuse driver circuit in both undervoltage and overvoltage conditions. Other embodiments are also described.

Fuse driver circuits

VBUS power switch

This document discusses, among other things, security measures for shielding or protecting data or sensitive signals on an integrated circuit (IC). The systems and methods disclosed herein can allow erasing sensitive data when access is not locked, locking out access to sensitive data during normal operations through both indirect and direct means, and shielding sensitive signals from invasive probing or manipulation.

Security measures for data protection

In one general aspect, a repeater can include an input terminal configured to be coupled to a first portion of a MIPI signal path. The MIPI signal path being a unidirectional path between a receiver and a transmitter, the input terminal configured to receive a set of signals from the receiver via the MIPI signal path. The repeater can include an output terminal configured to be coupled to a second portion of the MIPI signal path, the first portion of the MIPI signal path and the second portion of the MIPI signal path having a combined distance greater than 30 centimeters.

Methods and apparatus related to a repeater

This document discusses, among other things, a control circuit, such as a translator circuit, configured to reduce voltage stress of first and second transistors when a first voltage received by the first transistor exceeds a voltage rating of at least one of the first or second transistors.

Growing community of inventors

Falmouth, ME, United States of America

Kenneth Patrick Snowdon