Motorola Corporation

Freescale Semiconductor,inc.

Kenneth P Tumin

Marlan L Winter

Steven P Lindquist

Dale John McQuirk

Alan Joseph Carlin

George E Baker

Hubert Glenn Carson, Jr

Matthew G Stout

Alex S Y Koh

A design-for-test (DFT) circuit for an integrated circuit (IC) for enabling accurate quiescent current testing. The IC includes a voltage supply pin, a ground pin and an internal voltage regulator coupled between the voltage supply and ground pins for providing an internal output voltage. The DFT circuit includes a voltage storage device which couples to the voltage regulator to temporarily maintain the internal output voltage when the voltage regulator is disabled. The mode control circuit detects a quiescent current test mode, disables the voltage regulator and decouples the voltage regulator from the voltage storage device when the quiescent current test mode is detected. The DFT circuit may include an enable circuit which generates a freeze signal when the quiescent current test mode is detected, and at least one switch which decouples the voltage regulator from the voltage storage node. The DFT circuit is particularly useful for low pin-count ICs.

Design-for-test circuit for low pin count devices

A test pattern generation flow has a stimulus and a device under test (DUT) that operate together through a test bench. The test bench monitors and collects all the data necessary to generate a test program. This information is presented as a captured simulation that allows for ease of generating test software, as well as other simulations such as fault simulation and virtual test simulation. The complete and convenient information can be utilized to automate the development and/or easily manually develop and debug the test software.

Method for producing test patterns for testing an integrated circuit

A simulation input and a model file are generated. The simulation input file is processed to generate object code, entries, line counts, and comment lines. A simulation program is run that uses the object code, entries, line counts, and input comment lines. A machine captures and links output comment lines with their associated test vectors by using the entries and line counts to form a simulation results file. After the simulation, the simulation results file can be reviewed. After simulation, masks (30, 40, 50, 60, 70) are generated that are used to form integrated circuits (20). The present invention can also be used for testing integrated circuits. The test methods use a test input file generated from the simulation results file.

Methods of simulating an electronic circuit design

Method of forming an integrated circuit

During an electronic circuit simulation, an input file is generated that has source code and stimulus sections. Each of the source code and stimulus sections includes linking portions that each link a portion of the source code to a portion of the stimulus sections. The input file is processed to generate object code and a stimulus file that includes linking portions. The linking portions of the stimulus file allow events to occur that are synchronized with the object code during the running of a simulation program. The linking between the stimulus file and the object code is synchronized because the stimulus file is generated from the input file that has the linking portions. The linking remains synchronized even if the input file is modified. After a simulation, masks (30, 40, 50, 60, 70) can be generated and used to form an integrated circuit (20).

Methods of simulating an electronic circuit design and forming an

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Austin, TX, United States of America

Kenneth P Tumin