Hyundai Electronics America, Inc.

Lsi Logic Corporation

At&t Global Information Solutions Company

Other

Ncr Corporation

Symbios Logic Inc.

Kenneth P Fuchs

Gayle W Miller

Derryl D J Allman

Samuel C Gioia

Derryl D Allman

Todd A Randazzo

Steven S Lee

John De Q Walker

A process for forming a capacitive structure that includes an upper layer having a first capacitor electrode section therein. A capacitor dielectric layer is formed adjacent the upper layer. The capacitor dielectric layer covers the first capacitor electrode section. A second capacitor electrode layer is formed adjacent the capacitor dielectric layer. The second capacitor electrode layer includes a second capacitor electrode section that at least partially covers the first capacitor electrode section, and which has an edge portion that extends beyond the underlying first capacitor electrode section. The capacitor dielectric layer being disposed between the first capacitor electrode section and the second capacitor electrode section. An upper dielectric layer is formed adjacent the second capacitor electrode section. Portions of the upper dielectric layer and the second capacitor electrode section are selectively removed to form a first via cavity that extends through the upper dielectric layer and the edge portion of the second capacitor electrode section. This exposes the edge portion of the second capacitor electrode section within the first via cavity. The first via cavity is filled with a via metal, which makes electrical connection with the edge portion of the second capacitor electrode section that is exposed within the first via cavity.

Analog capacitor in dual damascene process

A metal-insulator-metal capacitor is embedded in an interconnect layer of an integrated circuit (IC). The interconnect layer has a cavity, and the capacitor is formed in the cavity with one of the plates of the capacitor integral with a conductive layer of the interconnect layer, so the capacitor plate electrically communicates with the interconnect layer. The interconnect layer has multiple conductive layers, including a layer, such as aluminum, that is subject to deformation at certain temperatures during fabrication of the IC, and the cavity extends through this layer. A remaining conductive layer of the interconnect layer defines one of the capacitor plates, and a dielectric layer and another capacitor plate are formed thereon within the cavity. Via interconnects of about the same length electrically connect to the top plate and through the interconnect layer to the bottom plate.

Method of forming a metal-insulator-metal capacitor in an interconnect cavity

Method of forming analog capacitor dual damascene process

A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.

Integrated circuit device comprising low dielectric constant material for reduced cross talk

Low dielectric constant material in integrated circuit

Integrated circuit device with reduced cross talk

Interconnect-embedded metal-insulator-metal capacitor

Method for using low dielectric constant material in integrated circuit fabrication

A vertically oriented metal circuit element is electrically connected and isolated between vertically separated conductors of interconnect layers in an integrated circuit. The methodology involves connecting a lower end of the metal element to the lower interconnect layer at the lower end of an opening in an inter-layer dielectric, preferably by simultaneously forming the metal element and connecting it to the conductor by vapor deposition. An upper end of the metal element initially extends above an upper surface of the inter-layer dielectric, and chemical mechanical polishing is employed to reduce the upper end to a level flush with the upper surface of the inter-layer dielectric. The flush upper end of the metal element allows it to be precisely spaced and covered with dielectric material to obtain predictable and reliable electrical isolation characteristics. The electrical connection and isolation is obtained with a minimum of space to allow the metal element to the effectively positioned vertically between the interconnect layers.

Method of electrically connecting and isolating components with vertical elements extending between interconnect layers in an integrated circuit

The present invention applies a silicon nitride or the like as a mask over portions of a substrate, such as an active region, where oxide growth is undesired. Thereafter, without the formation of a recess in the substrate, a high pressure oxidation process is used to grow an oxide, preferably in a furnace. The oxide thus grows into the non-masked areas of the substrate, as well as over the silicon nitride used as a mask. Thereafter, a chemical-mechanical polish is used to etch away undesired oxide, with the silicon nitride being used as an endpoint to terminate the polish operation.

Isolation method utilizing a high pressure oxidation

A linear capacitor formed in an IC which has horizontally oriented interconnect layers that are vertically separated by dielectric material. Two separated metal plates of the capacitor are electrically connected to the conductors of different vertically-separated metal interconnect layers. The metal plates extend substantially vertically through the thicker dielectric material separating the interconnect layers, to provide a relatively high capacitance per unit of surface consumed. The interconnect layers to which the plates are connected are separated from a substrate of the IC by at least one layer of dielectric, to reduce parasitic effects. Forming the capacitor plates and the interconnect layers from at least some of the same metals simplifies construction and reduces cost, while providing linear response characteristics. Placing the capacitor between the interconnect layers avoids consuming space on the substrate to construct the capacitor.

High aspect ratio, metal-to-metal, linear capacitor for an integrated

A method for planarizing the surface of a semiconductor device which employs spin on glass (SOG) and an etching operation to remove high portions of the SOG prior to a chemical metal polish (CMP) operation. The SOG is baked and cured before etching. Additional layers of SOG and etching operations may be employed as necessary. A thick encapsulating oxide layer is deposited over the SOG layer. For surface irregularities caused by metal lines, an insulating layer may be deposited over the surface before the SOG. Where an additional metal line is to be deposited on the surface, an additional insulating layer is deposited after the CMP operation. In the case of metal lines made of aluminum, provision is also made for preventing Hillock formations on the metal lines.

Growing community of inventors

Colorado Springs, CO, United States of America

Kenneth P Fuchs