International Business Machines Corporation

Lenovo (Singapore) Pte. Ltd.

Kenneth Michael Valk

Fredy Daniel Neeser

Claude Basso

Mircea R Gusat

Cyriel Johan Minkenberg

Nikolaos Chrysos

David Alan Shedivy

Michael Steven Siegel

William John Starke

Jeffrey A Stuecheli

Lakshminarayana Baba Arimilli

John David Irish

Rolf Clauberg

Casimer M DeCusatis

Bartholomew Blaner

William Joseph Armstrong

Bruce Marshall Walk

Russell Dean Hoover

Brian Thomas Vanderpool

Thomas R Sand

Wayne Melvin Barrett

Keshav G Kamble

Chih-Jen Chang

David R Engebretsen

Bruce Leroy Beukema

William Thomas Flynn

Phillip Rogers Hillier, Iii

Derek E Williams

Josep Cors

Kyle Alan Lucke

David John Krolak

George Wayne Nation

Curtis Carl Wollbrink

Yiyu L Chen

Richard B Booth

Ronald Peter Luijten

Marcy Evelyn Byers

Guy L Guthrie

Daniel Mark Dreps

Eric Oliver Mejdrich

Gregory Michael Nordstrom

Ronald Edward Fuhs

Timothy Roy Block

Jeffrey Douglas Brown

Philip Rogers Hillier, Iii

Todd Alan Greenfield

James Francis Mikos

Jeffrey James Lynch

Yiftach Benjamini

Daniel Crisan

Delbert Raymond Cecchi

Lonny Lambrecht

Curtis Walter Preuss

Mark L Rudquist

Richard Charles Booth

Marius V Dina

In a data processing environment, a communication interface of a second host data processing system receives, from a first host data processing system, a host command in a first command set. The host command specifies a memory access to a memory coupled to the second host data processing system. The communication interface translates the host command into a command in a different second command set emulating coupling of an attached functional unit to the communication interface. The communication interface presents the second command to a host bus protocol interface of the second host data processing system. Based on receipt of the second command, the host bus protocol interface initiates, on a system fabric of the second host data processing system, a host bus protocol memory access request specifying the memory access.

Multifunction communication interface supporting memory sharing among data processing systems

An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an accelerator functional unit and an effective address-based accelerator cache for buffering copies of data from the system memory of the coherent data processing system, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit includes request logic that, responsive to receipt on the first communication interface of a translation entry invalidation request, issues to the accelerator unit via the second communication interface an invalidation request that identifies an entry in the effective address-based accelerator cache to be invalidated utilizing a host tag identifying a storage location in the real address-based directory.

Translation invalidation in a translation cache serving an accelerator

IEEE 802.1Q and Enhanced Transmission Selection provide only eight different traffic classes that may be used to control bandwidth in a particular physical connection (or link). Instead of relying only on these eight traffic classes to manage bandwidth, the embodiments discussed herein disclose using an Enhanced Transmission Selection scheduler that permits a network device to set the bandwidth for an individual virtual LAN. Allocating bandwidth in a port based on a virtual LAN ID permits a network device to allocate bandwidth to, e.g., millions of unique virtual LANs. Thus, this technique may increase the granular control of the network fabric and its performance.

Flexible and scalable enhanced transmission selection method for network fabrics

An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from a system memory, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit further includes request logic that communicates memory access requests and request responses with the accelerator unit. The request logic, responsive to receipt from the accelerator unit of a read-type request specifying an aliased second effective address of a target cache line, provides a request response including a host tag indicating that the accelerator unit has associated a different first effective address with the target cache line.

Integrated circuit and data processing system supporting address aliasing in an accelerator

An integrated circuit for a coherent data processing system includes a first communication interface for communicatively coupling the integrated circuit with the coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from a system memory of the coherent data processing system, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit further includes request logic that communicates memory access requests and request responses with the accelerator unit via the second communication interface. A request response identifies a target of a corresponding memory access request utilizing a host tag specifying an entry associated with the target in the real address-based directory.

Integrated circuit and data processing system supporting attachment of a real address-agnostic accelerator

In one embodiment, a method includes receiving a plurality of flows, each flow comprising packets of data and assigning a service credit to each of the plurality of flows. In addition, the method includes assigning a weight parameter to each of the plurality of flows, and selecting a flow from a head of a first control queue unless the first control queue is empty or there is indication that the first control queue should be avoided. A flow is selected from a head of a second control queue in response to a determination that the first control queue is empty or there is indication that the first control queue should be avoided. Additionally, the method includes providing a number of units of service to the selected flow. Moreover, the method includes decreasing the selected flow's service credit by an amount corresponding to the number of units of service provided thereto.

Arbitration of multiple-thousands of flows for convergence enhanced ethernet

An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from a system memory, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit further includes directory control logic that configures at least a number of congruence classes utilized in the real address-based directory based on configuration parameters specified on behalf of or by the accelerator unit.

Integrated circuit and data processing system having a configurable cache directory for an accelerator

A claw-back request, received from an accelerator, is issued for an address line. While waiting for a response to the claw-back request, a cast-out push request with a matching address line is received. The cast-out push request is associated with a cache having a modified copy of the address line. A combined-response, associated with the cast-out push request, is received from a bus. Data associated with the modified copy of the address line is received from the cache. A claw-back response, with the data associated with the modified version of the address line, is issued to an accelerator.

Accelerator memory coherency with single state machine

A serial communication system includes a transmitting circuit for serially transmitting data via a serial communication link including N channels where N is an integer greater than 1. The transmitting circuit includes an input buffer having storage for input data frames each including M bytes forming N segments of M/N contiguous bytes. The transmitting circuit additionally includes a reordering circuit coupled to the input buffer. The reordering circuit includes a reorder buffer including multiple entries. The reordering circuit buffers, in each of multiple entries of the reorder buffer, a byte in a common byte position in each of the N segments of an input data frame. The reordering circuit sequentially outputs the contents of the entries of the reorder buffer via the N channels of the serial communication link.

Pre-transmission data reordering for a serial interface

In one embodiment, a method includes selecting a flow from a head of a first control queue or a second control queue. The method also includes providing service to the selected flow. Moreover, the method includes decreasing a service credit of the selected flow by an amount corresponding to an amount of service provided to the selected flow. In another embodiment, a computer program product includes a computer readable storage medium having program code embodied therewith. The embodied program code is readable/executable by a device to select, by the device, a flow from a head of a first control queue or a second control queue. The embodied program code is also readable/executable to provide, by the device, service to the selected flow, and decrease, by the device, a service credit of the selected flow by an amount corresponding to an amount of service provided to the selected flow.

A method for synchronizing multicast message subflows in a switched network includes associating, with a processing device, a first destination identifier corresponding to a multicast message with a first queue that corresponds to a first output port of a switching device, associating, with a processing device, a second destination identifier corresponding to the multicast message with a second queue that corresponds to a second output port of the switching device, pausing the first queue in response to a message counter corresponding to the first queue crossing a first predetermined threshold, and unpausing the first queue in response to the message counter crossing a second predetermined threshold, wherein the message counter indicates a quantity of data that has been forwarded by the first queue but remains to be forwarded by the second queue.

Computer-based flow synchronization for efficient multicast forwarding for products and services

A network fabric may divide a physical connection into a plurality of VLANs as defined by IEEE 802.1Q. Moreover, many network fabrics use Priority Flow Control to identify and segregate network traffic based on different traffic classes or priorities. Current routing protocols define only eight traffic classes. In contrast, a network fabric may contain thousands of unique VLANs. When network congestion occurs, network devices (e.g., switches, bridges, routers, servers, etc.) can negotiate to pause the network traffic associated with one of the different traffic classes. Pausing the data packets associated with a single traffic class may also stop the data packets associated with thousands of VLANs. The embodiments disclosed herein permit a network fabric to individually pause VLANs rather than entire traffic classes.

Flexible and scalable data link layer flow control for network fabrics

In one embodiment, a system includes a processor and logic integrated with and/or executable by the processor, the logic being adapted to: receive a plurality of flows, each flow comprising packets of data, assign a service credit to each of the plurality of flows, assign a weight parameter to each of the plurality of flows, select a flow from a head of a first control queue unless the first control queue is empty or there is indication that the first control queue should be avoided, wherein a flow is selected from a head of a second control queue when the first control queue is empty or there is indication that the first control queue should be avoided, provide a number of units of service to the selected flow, and decrease the selected flow's service credit by an amount corresponding to the number of units of service provided thereto.

A system for hierarchical occupancy based congestion management includes a buffer embodied in a computer readable storage medium including a plurality of buffer units for storing packets of a data flow received from sources. The system includes a buffer manager that stores information about the packets stored in the buffer, including a selection criterion associated with each of the plurality of sources and a congestion estimator that monitors a congestion level in the buffer. The system also includes a occupancy sampler that randomly selects at least two occupied buffer units from the plurality of buffer units and identifies the source of the packet stored in each of the occupied buffer units and a congestion notification message generator that generates a congestion notification message; wherein if the congestion level in the buffer exceeds a threshold value the congestion notification message is sent to the identified source with a higher selection criteria.

Hierarchical occupancy-based congestion management

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Rochester, MN, United States of America

Kenneth Michael Valk