Cadence Design Systems, Inc.

Kenneth Mednick

Roland Ruehl

Eitan Cadouri

Xiaojun Wang

Haifang Liao

Krzysztof Antoni Kozminski

Mark A Snowden

Disclosed is an improved method and system for processing the tasks performed by an EDA tool in parallel. The IC layout is divided into a plurality of layout windows and one or more of the layout windows are processed in parallel. Sampling of one or more windows may be performed to provide dynamic performance estimation.

Method and system for implementing parallel processing of electronic design automation tools

Responding to a single command, a layout versus schematic (LVS) tool processes layout data describing positions of conductors on layers of an IC to produce data representing a shape recognition layer depicting boundary shapes of spirals of drawn inductors. The boundary shape of a spiral is the shape of the spiral as viewed from above with all of the layers of conductive material forming the spiral superimposed. The LVS tool then processes the shape recognition layer data to identify the type and position of each drawn inductor, to determine whether each inductor's spiral turns are of uniform width and spacing, to detect connectivity violations, and to determine parameters relating to the shape of the spiral from which its inductance can be computed.

IC layout physical verification method

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San Jose, CA, United States of America

Kenneth Mednick