Hewlett-packard Development Company, L.P.

Other

Hewlett-packard Company

Hewlett-packard Development, L.p.

Kenneth Mark Wilson

Robert Bruce Aglietti

Lance Warren Russell

Fong Pong

Tung M Nguyen

Sumit Roy

Lu Xu

Yoshio Frank Turner

Rajendra Kumar

Paul S Keltcher

Thomas Lee Watson

Prashanth Balakrishna Bhat

Milos Prvulovic

John C Colwill

Surgical implants for neighboring bones are disclosed herein. Preferred implants are configured to be implanted into the scaphoid and lunate. Preferred implants include a first plate configured to be implanted into the scaphoid and a second plate configured to be implanted into the lunate wherein said first and second plates are couple together by a rotatable rod.

Scapho-lunate fixation implants and methods of use

A method for inline bus data compression and decompression is disclosed. In one embodiment, data is selected for transfer via a data bus, the data is divided into byte sized divisions of the bus width, and each byte is compressed by an individual compression engine. The data is then properly sequenced, aligned and recombined and further transmitted in its compressed state. When required to be decompressed, the compressed data is again divided into bytes of compressed data, each byte being decompressed individually, and then restored to the bus in its uncompressed form, in essence, in the reverse order of the compression process.

Method for improving inline compression bandwidth for high speed buses

A cache coherent distributed shared memory multi-processor computer system is provided with a memory controller which includes a recall unit. The recall unit allows selective forced write-backs of dirty cache lines to the home memory. After a request is posted in the recall unit, a recall ('flush') command is issued which forces the owner cache to write-back the dirty cache line to be flushed. The memory controller will inform the recall unit as each recall operation is completed. The recall unit operation will be interrupted when all flush requests are completed.

Multi-processor computer system with cache-flushing system using memory recall

The present invention, in various embodiments, provides techniques for managing memory in computer systems. One embodiment uses a memory table having entries to locate data residing in different types of storage areas, such as physical memory, hard disc, file servers, storage devices, etc. Upon a program accessing memory for a particular piece of data, the memory table translates the data's physical address to an address used to find the table entry pointing to the requested data. In one embodiment, if the data is in physical memory, then the requested data is returned to the program. However, if the data is not in physical memory and it is determined that the data will be used frequently, then the data, in addition to being returned, is also brought to the physical memory for later use. This is because accessing the data from physical memory usually takes less time than accessing the data from other storage devices.

Memory table and memory manager for use in managing memory

In a method for optimizing performance in a memory system, a data structure configured to provide at least one free block of memory is received in the memory system. At least one bucket of memory is released in a swap device of the memory system corresponding to at least one free block of memory provided by the data structure.

Efficiency in a memory management system

The present invention, in various embodiments, provides techniques for managing latencies in accessing memory of computer systems. In one embodiment, upon accessing the memory system for a piece of data used by a first process, a latency manager determines the access time to acquire the piece of data in the memory system. The latency manager then compares the determined access time to a threshold. If the determined access time is greater than the threshold, the latency manager triggers an interrupt for the operating system to switch threads or processes so that execution of the first process is postponed and execution of a second process starts. Various embodiments include the latency manager is polled for the access time when the processor is stalled, the latency manager triggers a process switch when a particular memory subsystem is accessed, etc.

Managing latencies in accessing memory of computer systems

A method and system providing dynamic allocation of memory through hardware is disclosed. An embodiment provides for a multi-processor system providing for a secure partitioned memory. The system comprises a processor(s), a hardware implemented memory router coupled to the processor(s), and memory coupled to the memory router. The memory router stores memory partition information, which describes the memory allocated to the processor(s). Furthermore, the memory router maps a memory access request from a processor to an address in the memory.

Method and system for creating secure address space using hardware memory router

A multi-processor system using distributed memory is provided with a cache of history counters located within each memory controller. Each entry of the cache of history counters represents one page in memory that has the potential to increase system performance by migrating or replicating to other memory locations. The cache of history counters permits creating histories of local memory accesses by remote processors for purposes of dynamic page placement.

Computer architecture with caching of history counters for dynamic page placement

The present invention pertains to a system for performing data compression/decompression. The system may have a memory controller with compression/decompression logic. A first memory array may be coupled to the memory controller via a first bus and a second memory array may be coupled to the memory controller via a second bus. The system may also have logic for directing the transfer of data from the first memory array via the first bus to be processed by the compression/decompression logic and then transferred to the second memory array via the second bus.

System for compressing/decompressing data

The present invention, in various embodiments, provides techniques for managing memory in computer systems. In one embodiment, each memory page is divided into relocation blocks located at various physical locations, and a relocation table is created with entries used to locate these blocks. To access memory for a particular piece of data, a program first uses a virtual address of the data, which, through a translation look-aside buffer, is translated into a physical address within the computer system. Using the relocation table, the physical address is then translated to a relocation address that identifies the relocation block containing the requested data. From the identified relocation block, the data is returned to the program.

Relocation table for use in memory management

An apparatus for and a method of memory-affinity process scheduling in CC-NUMA systems. The system includes a plurality of nodes connected to a network. A plurality of processes are running on the various nodes of the system. The system further includes at least one memory-affinity counter for each executing process for each node of the system. Process scheduling begins by assigning processes to nodes. During execution, the memory-affinity counters are incremented on every memory access. At a process rescheduling interval, the memory-affinity counters are evaluated and rescheduling is performed based on a preselected policy. At a reset interval, the memory-affinity counters are adjusted to reduce the impact of older memory accesses. The resulting memory-affinity process scheduling is NUMA aware.

Apparatus for and method of memory-affinity process scheduling in CC-NUMA systems

A multiprocessor system, where the latencies to access areas of memory have different values, provides the capability of having the operating system use large page sizes while dynamic page placement manipulates subsets of the large pages without affecting translation look-aside buffers in the processors. A sub-page support structure is inserted between the processor and the network interface to remote memory that on a remote memory access determines if a local copy of the data exists and, if it does, to change the remote access to a local access. Where a sub-page in a remote memory has been migrated to a third UMA cell, the sub-page support structure also instructs the processor of the new memory location or passes the access along to the correct UMA cell.

Computer architecture with dynamic sub-page placement

A processor having one or more address translation registers for holding translation information that enables translations from virtual addresses to physical addresses. The address translation registers may be allocated to a set of logical areas of a process and the logical areas may be allocated to physical pages so as to enhance a likelihood that translation information for the process will be available in the address translation registers. The address translation registers are saved and restored during context switches. The address translation registers may be used with or without translation look-aside buffers.

Processor with a general register set that includes address translation registers

A method is provided for cache flushing in a computer system having a processor, a cache, a synchronization primitive detector, and a cache flush engine. The method includes providing a synchronization primitive from the processor into the computer system; detecting the synchronization primitive in the synchronization primitive detector; providing a trigger signal from the synchronization primitive detector in response to detection of the synchronization primitive; providing cache information from the recall unit into the computer system in response to the trigger signal; and flushing the cache in response to the cache information in the computer system.

Multi-processor computer system with lock driven cache-flushing system

A cache coherent distributed shared memory multi-processor computer system is provided with a memory controller which includes a recall unit. The recall unit allows selective forced write-backs of dirty cache lines to the home memory. After a request is posted in the recall unit, a recall (&ldquo;flush&rdquo;) command is issued which forces the owner cache to write-back the dirty cache line to be flushed. The memory controller will inform the recall unit as each recall operation is completed. The recall unit operation will be interrupted when all flush requests are completed.

Growing community of inventors

San Jose, CA, United States of America

Kenneth Mark Wilson