Newport Fab, LLC

Kenneth M Ring

Amol M Kalburge

Kevin Q Yin

Paul D Hurwitz

Chun Hu

David J Howard

Dieter Dornisch

Tinghao Frank Wang

Guangming Li

According to one exemplary embodiment, a bipolar transistor includes a base having a top surface. The bipolar transistor further includes a base oxide layer situated on the top surface of the base. The bipolar transistor further includes an antireflective coating layer situated on the base oxide layer. The bipolar transistor further includes an emitter situated over the top surface of the base and the antireflective coating layer, where a layer of polysilicon is not situated between the base oxide layer and the emitter.

Bipolar transistor fabricated in a biCMOS process

According to one exemplary embodiment, a method for forming an NPN and a vertical PNP device on a substrate comprises forming an insulating layer over an NPN region and a PNP region of the substrate. The method further comprises forming a buffer layer on the insulating layer and forming an opening in the buffer layer and the insulating layer in the NPN region, where the opening exposes the substrate. The method further comprises forming a semiconductor layer on the buffer layer and in the opening in the NPN region, where the semiconductor layer has a first portion situated in the opening and a second portion situated on the buffer layer in the PNP region. The first portion of the semiconductor layer forms a single crystal base of the NPN device and the second portion of the semiconductor layer forms a polycrystalline emitter of the vertical PNP device.

Method for integrating SiGe NPN and vertical PNP devices

Integration of SiGe NPN and vertical PNP devices on a substrate

According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a base oxide layer situated on top surface of the base. The bipolar transistor further comprises a sacrificial post situated on base oxide layer. The bipolar transistor further comprises a conformal layer situated over the sacrificial post and top surface of the base, where the conformal layer has a density greater than a density of base oxide layer. The conformal layer may be, for example, HDPCVD oxide. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer. The sacrificial planarizing layer has a first thickness in a first region between first and second link spacers and a second thickness in a second region outside of first and second link spacers, where the second thickness is generally greater than the first thickness.

Fabricating a self-aligned bipolar transistor having increased manufacturability

According to one embodiment of the invention, a method for fabricating a MIM capacitor in a semiconductor die includes a step of depositing a first interconnect metal layer. The method further includes depositing a layer of silicon nitride on the first interconnect layer. The layer of silicon nitride is deposited in a deposition process using an ammonia-to-silane ratio of at least 12.5. The method further includes depositing a layer of MIM capacitor metal on the layer of silicon nitride. The method further includes etching the layer of MIM capacitor metal to form an upper electrode of the MIM capacitor. According to this exemplary embodiment, the method further includes etching the layer of silicon nitride to form a MIM capacitor dielectric segment and etching the first interconnect metal layer to form a lower electrode of the MIM capacitor. The MIM capacitor has a capacitance density of at least 2.0 fF/um.

Method for fabricating a MIM capacitor having increased capacitance density and related structure

Self-aligned bipolar transistor having increased manufacturability

According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a base oxide layer situated on top surface of the base. The bipolar transistor further comprises a sacrificial post situated on the base oxide layer. The bipolar transistor further comprises a conformal layer situated over the sacrificial post and top surface of the base, where the conformal layer has a density greater than a density of the base oxide layer. The conformal layer may be, for example, HDPCVD oxide. According to this exemplary embodiment, the bipolar transistor further comprises a sacrificial planarizing layer situated over the conformal layer. The sacrificial planarizing layer has a first thickness in a first region between first and second link spacers and a second thickness in a second region outside of first and second link spacers, where the second thickness is generally greater than the first thickness.

Method for fabricating a self-aligned bipolar transistor having increased manufacturability and related structure

Method for integrating SiGe NPN and vertical PNP devices on a substrate and related structure

According to one exemplary embodiment, a method for fabricating a bipolar transistor in a BiCMOS process comprises a step of forming an emitter window stack by sequentially depositing a base oxide layer and an antireflective coating layer on a top surface of a base, where the emitter window stack does not comprise a polysilicon layer. The method further comprises etching an emitter window opening in the emitter window stack. The method further comprises depositing an emitter layer in the emitter window opening and over the antireflective coating layer and etching the emitter layer to form an emitter. The method further comprises etching a first portion of the base oxide layer not covered by the emitter using a first etchant, thereby causing the first portion of the base oxide layer to have a thickness less than a thickness of a second portion of the base oxide layer covered by the emitter.

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Tustin, CA, United States of America

Kenneth M Ring