Texas Instruments Corporation

Kenneth M Bell

Joe R Trogolo

Shivaling S Mahant-Shetti

Lars Risbo

Venkateswar Reddy Kowkutla

Sami Kiriaki

William H Giolma

Luis Eduardo Ossa

Shifeng Zhao

Anker Josefsen

Michael R Seacrist

Shigeng Zhao

A digital amplifier includes a noise shaper and a dither generator arranged to introduce noise to the shaper. The generator uses a seed value derived from a state variable of the shaper.

Amplifiers

A metal-oxide-semiconductor digital-to-analog converter unit includes a multiplicity of current mirror components 20 in a symmetric array, a resistance network activated by voltage sources providing weighted biasing potentials for the current mirror components, and an electrical coupling of the current mirror components to compensate for variations physical properties across converter unit substrate area. The current mirror components 20 include a current steering portion 21.sub.0 -21.sub.N-1 and 25.sub.0 -25.sub.N-1 coupled to an annular bias transistor 22. The resulting digital-to-analog converter has improved performance characteristics when compared to previously implemented digital-to-analog converter units.

Apparatus and method for current steering digital-to-analog converter

A circuit technique for biasing a complementary NPN-PNP Darlington Emitter Follower Stage without additional biasing resistors or current sources. Four diode-connected transistor are connected in series to provide biasing across the Darlington. Two transistors, one NPN and one PNP, are added with their bases and emitters connected in parallel with the top and bottom diodes, respectively, forming two current mirrors. The collector of the NPN transistor connects to the emitter of the first Darlington NPN transistor. The collector of the PNP transistor connects to the first Darlington PNP transistor. The current mirrors provide equal current to the two first Darlington transistors. These currents are also equal to the current through the four diodes for identically sized transistors.

Circuit technique for biasing complementary Darlington emitter follower

A unified process flow for the fabrication of an isolated vertical PNP (VPNP) transistor, a junction field effect transistor (JFET) and a metal/nitride/polysilicon capacitor includes the simultaneous fabrication of deep junction isolation regions (36, 121) and a VPNP buried collector (28). Junction isolation is completed by the doping and diffusion of shallow junction isolation regions (46, 122) at the same time that deep collector regions (48) are formed. A JFET source region (74) and a drain region (76) are formed simultaneously with a VPNP emitter region (70). A JFET gate contact region (88) is formed simultaenously with a VPNP base contact region (84), a VPNP buried region contact (86) and optionally with the doping of a capacitor electrode (124).

Process for fabricating isolated vertical bipolar and JFET transistors

One of the input and output terminals of a current amplifier is coupled via a threshold conduction device to a drive circuit input terminal and the other of the input and output terminals is coupled via the conduction path of an output transistor to an output terminal of the drive circuit. A further amplifier, coupled to the threshold conduction device, provides a low impedance drive signal for the control electrode of the output transistor for biasing the output transistor to produce an output current proportional to an input current applied to the drive circuit input terminal and for enhancing the transient recovery time of the drive circuit for abrupt changes in output voltage at the output terminal.

Constant current drive circuit with reduced transient recovery time

A clamp circuit which breaks down under application of high voltage is connected to an input pin to be protected through a unidirectional device such as a diode. A voltage supply is connected to the discharge path between the unidirectional device and the clamp. The voltage supply will therefore supply any leakage currents which may be drawn by the clamp during normal operation.

ESD input protection circuit

A buried n-channel junction field-effect transistor (JFET) fabricated in standard bipolar integrated circuit starting material. The transistor has a deep p-well as the bottom gate formed in an n-type body. The source is surrounded by the p-well while the drain is the epitaxial layer near the surface of the body outside the p-well. A buried channel connects the source and drain. A p-layer above the buried channel forms the top gate. Gate leakage current and noise are very low.

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Windom, TX, United States of America

Kenneth M Bell