International Business Machines Corporation

Other

Kenneth Lundy Ward

Dung Q Nguyen

Susan Elizabeth Eisen

Glenn Owen Kincaid

Christopher M Mueller

Hung Qui Le

Deepak K Singh

Brian William Thompto

Brian David Barrick

David Allen Hrusecky

Albert James Van Norstrand, Jr

Scott Barnett Swaney

Joe Lee

Kurt Alan Feiste

Michael Joseph Genden

Steven J Battle

Tobias Webel

Ulrich Weiss

Michael James Mack

Matthias Woehrle

Bryan J Lloyd

Maarten Jakob Boersma

Robert Allen Cordes

Dhivya Jeganathan

Gaurav Mittal

A James Van Norstrand, Jr

Jennifer L Molnar

Eula Faye Abalos Tolentino

Balaram Sinharoy

Jing Zhang

Sundeep Chadha

Richard Louis Arndt

Christian Zoellin

David R Terry

Salma Ayub

Andreas Wagner

Cliff Kucharski

Tu-An T Nguyen

David S Walder

Kent Li

Amit Sumanlal Shah

Steven Russell Barnhart

George M Jameson, Sr

Method and apparatus for a completion mechanism for a microprocessor are provided by identifying entries in a section of an Instruction Completion Table (ICT) that are marked as ready to complete via corresponding Ready to Complete (RTC) status bits; determining a tail pointer indicating a start of the entries in the ICT that are ready for completion; determining a head pointer that indicates an end of the entries in the ICT that are ready for completion; completing instructions included in the entries between the tail pointer and the head pointer; and updating the tail pointer to a value of the head pointer for a subsequent instruction completion round.

Completion mechanism for a microprocessor instruction completion table

In at least one embodiment, a processor includes architected and non-architected register files for buffering operands. The processor additionally includes an instruction fetch unit that fetches instructions to be executed and at least one execution unit. The at least one execution unit is configured to execute a first class of instructions that access operands in the architected register file and a second class of instructions that access operands in the non-architected register file. The processor also includes a mapper circuit that assigns physical registers to the instructions for buffering of operands. The processor additionally includes a dispatch circuit configured, based on detection of an instruction in one of the first and second classes of instructions for which correct operands do not reside in a respective one of the architected and non-architected register files, to automatically initiate transfer of operands between the architected and non-architected register files.

Processor providing intelligent management of values buffered in overlaid architected and non-architected register files

A simultaneous multithreading processor and related method of operating are disclosed. The method comprises dispatching portions of a first instruction to be executed by a respective plurality of execution units of the processor; receiving, at an instruction completion table of the processor, respective finish reports responsive to execution of the portions of the first instruction; determining, using the received finish reports, that all of the portions of the first instruction have been executed; and updating the instruction completion table to indicate that the first instruction is ready for completion.

Finish status reporting for a simultaneous multithreading processor using an instruction completion table

A computer system, processor, and method for processing information is disclosed that includes at least one processor having a main register file, the main register file having a plurality of entries for storing data; one or more execution units including a dense math execution unit; and at least one accumulator register file, the at least one accumulator register file associated with the dense math execution unit. The processor in an embodiment is configured to process data in the dense math execution unit where the results of the dense math execution unit are written to a first group of one or more accumulator register file entries, and after a checkpoint boundary is crossed based upon, for example, the number 'N' of instructions dispatched after the start of the checkpoint, the results of the dense math execution unit are written to a second group of one or more accumulator register file entries.

Check pointing of accumulator register results in a microprocessor

A computer system includes a dispatch stage configured to dispatch a plurality of instructions in a program order, and an issue stage configured to issue at least one instruction among the plurality of instructions. The computer system further includes an execution stage configured to execute the at least one instruction to generate a finish report and to determine the at least one instruction is one of an exception-free instruction or an exception instruction. In response to determining the exception-free instruction, a first finish report associated with the exception-free instruction is output to a completion stage. In response to determining the exception instruction, a second finish report associated with the exception instruction is output to an exception unit so as to halt output of the second finish report to the completion stage.

Finish exception handling of an instruction completion table

A simultaneous multithreading processor is configured to select a first thread of the plurality of threads according to a predefined scheme, and access an instruction completion table to determine whether the first thread is eligible to have a first instruction prioritized. Responsive to determining that the first thread is eligible to have the first instruction prioritized, the simultaneous multithreading processor is further configured to execute the first instruction of the first thread using a dedicated prioritization resource.

Prioritized instructions in an instruction completion table of a simultaneous multithreading processor

Embodiments include systems, methods, and computer program products for using a multi-tier hang buster for detecting and breaking out of hang conditions in a processor. One method includes determining a plurality of actions available at each of a plurality of tiers used for breaking out of the hang condition in the processor. The method also includes, after detecting the hang condition on a first thread of the processor, performing one or more actions available at a first tier of the plurality of tiers to break out of the hang condition. The method further includes, after performing the one or more actions at the first tier and determining that the hang condition is still present, performing one or more actions available at one or more second tiers of the plurality of tiers to break out of the hang condition.

On-demand multi-tiered hang buster for SMT microprocessor

A computer-implemented method, computer program product, and computer processing system are provided. The method includes processing, by a superscalar processing pipeline, respective sets of instructions in respective instruction processing cycles using an Instruction Completion Table (ICT) with a Ready-To-Complete (RTC) vector. The ICT includes a plurality of entries, each corresponding to a respective one of the instructions. A Next-To-Complete (NTC) instruction from among the respective sets of instructions is computed using the RTC vector.

Instruction completion table with ready-to-complete vector

A computer system, processor, and method for processing information is disclosed that includes determining whether an instruction is a designated instruction, determining whether an instruction following the designated instruction is a subsequent store instruction, speculatively releasing the subsequent store instruction while the designated instruction is pending and before the subsequent store instruction is complete. Preferably, in response to determining that an instruction is the designated instruction, initiating or advancing a speculative tail pointer in an instruction completion table (ICT) to look through the instructions in the ICT following the designated instruction.

Speculatively releasing store data before store instruction completion in a processor

Systems, methods, and computer-readable media are described for performing speculative execution of both paths/branches of a weakly predicted branch instruction. A branch instruction may be fetched from an instruction queue and determined to be a weakly predicted branch instruction, in which case, both paths of the branch instruction may be dispatched and speculatively executed. When the actual path taken becomes known, instructions corresponding to the path not taken may be flushed. Instructions from both paths of a weakly predicted branch instruction that are speculatively executed may be dispatch and executed in an interleaved manner.

Speculative execution of both paths of a weakly predicted branch instruction

A computer system, processor, and method for processing information is disclosed that includes a Dispatch Unit for dispatching instructions; an Issue Queue for receiving instructions dispatched from the Dispatch Unit; and a queue for receiving instructions issued from the Issue Queue, the queue having a plurality of entry locations for storing data. In an embodiment instructions are dispatched with a virtual indicator, and the virtual indicator is set to a first mode for instructions dispatched where an entry location is available, and to a second mode where an entry location is not available, in the queue to receive the dispatched instruction. In addition to virtual tagging dispatched instructions, a system, processor, and method are disclosed for regional partitioning of queues, region based deallocation of queue entries, and circular thread based assignment of queue entries.

Dispatching, allocating, and deallocating instructions with real/virtual and region tags in a queue in a processor

Method and apparatus for completing atomic instructions in a microprocessor may be provided by identifying from a program-ordered Instruction Completion Table (ICT) a last entry in a completion window of instructions for completion in a current clock cycle of a processor; in response to determining that the last entry includes an atomic instruction that straddles the completion window: excluding the last entry from completion during the current clock cycle; completing instructions in the completion window for the current clock cycle; and shifting the completion window to include the last entry and a next entry adjacent to the last entry in the ICT in a next clock cycle.

Mechanism for completing atomic instructions in a microprocessor

Systems, methods, and computer program products are disclosed that control issuing branch instructions in a simultaneous multi-threading (SMT) system. An embodiment system includes an SMT processor circuit that receives, from one of a plurality of threads, a branch instruction having a favor bit. The SMT processor circuit schedules the branch instruction to issue, relative to branch instructions received from other threads in the plurality of threads, based on the favor bit. When the favor bit has a first value, the branch instruction is scheduled to have a higher priority to issue before the branch instructions received from other threads in the plurality of threads. When the favor bit has a second value, the branch instruction is scheduled to issue based an age of the branch instruction relative to respective ages of the branch instructions received from other threads in the plurality of threads.

Most favored branch issue

Systems, methods, and computer-readable media are described for performing instruction execution using an instruction completion table (ICT) that is configured to accommodate shared ICT entries. A shared ICT entry maps to multiple instructions such as, for example, two instructions. Each shared ICT entry may be referenced by an even instruction tag (ITAG) and an odd ITAG that correspond to respective instructions that have been grouped together in the shared ICT entry. The instructions corresponding to a given shared ICT entry can be executed and finished independently of one another. A shared ICT entry is completed when each execution of each instruction corresponding to the shared ICT entry has finished and when all prior ICT entries have completed. Also described herein are system, methods, and computer-readable media for flushing instructions in shared ICT entries in response to execution of a branch instruction.

Instruction completion table containing entries that share instruction tags

Method and apparatus for a completion mechanism for a microprocessor are provided by marking entries in a section of an Instruction Completion Table (ICT) as ready to complete using corresponding Ready to Complete (RTC) status bits; determining a tail pointer indicating a start of the entries in the ICT that are ready for completion in a current clock cycle; performing a counting leading ones on an RTC vector that organizes the RTC status bits according to a program order for completing the entries to determine a count leading ones pointer that indicates an end of the entries in the ICT that are ready for completion in the current clock cycle; completing instructions included in the entries between the tail pointer and the count leading ones pointer in one clock cycle; and updating the tail pointer to a value of the count leading ones pointer for a subsequent clock cycle.

Growing community of inventors

Austin, TX, United States of America

Kenneth Lundy Ward