Taiwan Semiconductor Manufacturing Comp. Ltd.

Kenneth Lin

Kuo-Wei Lin

James Chen

Chiou-Shian Peng

Alex Fahn

Gilbert Fane

Eugene Chu

Fu-Jier Fahn

Gilbert Fan

Eugene Cheu

Chien-Shian Peng

Euegene Chu

A method of making electrically conductive bumps of improved height on a semiconductor device. The method includes steps of depositing an under bump metallurgy over a semiconductor device onto a contact pad; depositing and patterning a photoresist layer to provide an opening over the under bump metallurgy; depositing a first electrically conductive material into the opening in the photoresist layer; depositing a second electrically conductive material over the first electrically conductive material; removing the photoresist layer and the excess under bump metallurgy; applying a flux agent to the top surface of the second electrically conductive material; hard baking the semiconductor device to remove any oxide; dipping a portion of the semiconductor device in an electroless plating solution; removing the semiconductor device from the electroless plating solution; and reflowing the electrically conductive materials to provide a bump of improved height on the semiconductor device.

Method of making tall flip chip bumps

Within a method for forming a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a patterned conductor layer having a topographic variation at a periphery of the patterned conductor layer. There is then formed over the substrate and passivating the topographic variation at the periphery of the patterned conductor layer a planarizing passivation layer formed of a thermally reflowable material. There is then formed upon the planarizing passivation layer a dimensionally stabilizing layer. Finally, there is then thermally annealed the microelectronic fabrication to form from the planarizing passivation layer a thermally annealed planarizing passivation layer. By employing formed upon the planarizing passivation layer the dimensionally stabilizing layer, there is attenuated within the thermally annealed planarizing passivation layer replication of the topographic variation at the periphery of the patterned conductor layer.

Patterned conductor layer pasivation method with dimensionally stabilized planarization

A method for removing a multiplicity of solder bodies connected to a semiconductor wafer through a copper wetting layer from the semiconductor wafer is disclosed. In the method, a semiconductor wafer that has on a top surface a multiplicity of solder bodies electrically connected to a multiplicity of bond pads through a multiplicity of copper wetting layers is first provided. When the multiplicity of solder bodies is found out of specification or must be removed for any other quality reasons, the semiconductor wafer is exposed to an etchant that has an etch rate toward the copper wetting layer at least 5 times the etch rate toward a metal that forms the multiplicity of bond pads. The semiconductor wafer may be removed from the etchant when the multiplicity of copper wetting layers is substantially dissolved such that the multiplicity of solder bodies is separated from the multiplicity of bond pads. The multiplicity of solder bodies may be either solder bumps or solder balls. The etchant may be a solution that contains Ce (NH,),(NO,),in a concentration range between about 3 wt. % and about 30 wt. % in water. Ultrasonic vibration may further be used to facilitate the dissolution of the copper wetting layers in the etchant.

Method for removing solder bodies from a semiconductor wafer

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Hsinchu, Taiwan

Kenneth Lin