International Business Machines Corporation

Globalfoundries Inc.

Kenneth Lee Wright

John Steven Dodson

Saravanan Sethuraman

Ravi Kumar Arimilli

Eric Eugene Retter

Derek E Williams

Luis Alfonso Lastras-Montano

Warren Edward Maule

Kyu-hyoun Kim

Robert Alan Cargnoni

Benjiman L Goodman

Joab Daniel Henderson

Marc Avery Gollub

Steven Robert Farago

Hillery C Hunter

Sanjeev Ghai

Stephen J Powell

Saurabh Chadha

Abhijit Saurabh

Paul William Coteus

Kevin Charles Gower

Karthick Rajamani

Diyanesh B Chinnakkonda Vidyapoornachary

Barry Marshall Trager

Michael Raymond Trombley

Shmuel Winograd

Robert James Ramirez

James Stephen Fields, Jr

Frank David Ferraiolo

Hugh Shen

Ramakrishnan Rajamony

Edgar Rolando Cordero

Venkatraghavan Bringivijayaraghavan

Charles Arthur Kilmer

Kevin Franklin Reick

Piyush Chunilal Patel

Hazim Shafi

Anil Bindu Lingambudi

Richard Nicholas

Brian John Connolly

Girisankar Paulraj

David Dean Sanner

Jeffrey A Sabrowski

Diyanesh B Vidyapoornachary

Steven J Hnatko

Vijay Anand Mathiyalagan

Ryan Joseph Pennington

Richard E Fry

Siva Rama K Pullelli

Walter R Lockwood

Guy L Guthrie

William John Starke

Balaram Sinharoy

Daniel Mark Dreps

Jason Raymond Baumgartner

Patrick James Meaney

Naresh Nayar

Ashish Jagmohan

Michele M Franceschini

Timothy Jay Dell

Robert Brett Tremaine

James A O'Connor

Gregory William Alexander

Malcolm Scott Allen-Ware

Adam J McPadden

Gregory Scott Still

Srinivasan Ramani

Todd Jon Rosedahl

Aaron C Brown

Todd Alan Venton

Michael B Spear

George William Daly, Jr

Jordan Ross Keuseman

Milton Devon Miller, Ii

Irving G Baysah

Sriram Srinivasan Mandyam

Daniel James Henderson

Paul Umbarger

Anton Blanchard

Michael J Mueller

John David McCalpin

Brett Adam St Onge

Lawrence Allyn McConville

Archie Don Barrett, Jr

Richard Nicolas

Kanwal Bahri

Dereck Edward Williams

Liang-Haw Leu

This disclosure includes a method for securing a memory of an electronic system that includes initializing the memory, creating a security key, transmitting the security key to memory, storing the security key in the memory, transmitting the current security key and a a new security key to the memory by the memory controller. If the current security key transmitted is the same as the security key stored in memory, then access to the memory is enabled and the current security key in the memory is replaced with the new security key. If the current security key transmitted is not the same as the security key stored in the memory, then access to the memory is disabled.

System for securing contents of removable memory

This disclosure includes a method for securing a memory of an electronic system that includes initializing the memory, creating a security key, transmitting the security key to memory, storing the security key in the memory, transmitting the current security key and a new security key to the memory by the memory controller. If the current security key transmitted is the same as the security key stored in memory, then access to the memory is enabled and the current security key in the memory is replaced with the new security key. If the current security key transmitted is not the same as the security key stored in the memory, then access to the memory is disabled.

A method provides processor initialization in different platform environments via a single code set. The method includes: in response to detecting a power-on operation of the processor, a microcontroller retrieving hardware procedures (HWP) framework code from a storage and triggering execution of the HWP framework code on the processor. The execution of the HWP framework code generates a HWP framework that comprises a plurality of application programming interfaces (APIs) which govern how all communication processes involving hardware procedures can be accomplished. The method further includes performing one or more initialization procedures by communicating one or more attribute data via the HWP framework to configure the processor for operation within a specific platform environment in which the processor is to be operated. The HWP framework includes standard interfaces and enables direct updates to hardware procedures without requiring a new flash code or a firmware patch.

Data driven hardware chips initialization via hardware procedure framework

A system and computer program product provide processor initialization in different platform environments via a single code set. The system includes: in response to detecting a power-on operation of the processor, a microcontroller retrieving hardware procedures (HWP) framework code from a storage and triggering execution of the HWP framework code on the processor. The execution of the HWP framework code generates a HWP framework that comprises a plurality of application programming interfaces (APIs) which govern how all communication processes involving hardware procedures can be accomplished. The system further includes the microcontroller performing one or more initialization procedures by communicating one or more attribute data via the HWP framework to configure the processor for operation within a specific platform environment in which the processor is to be operated. The HWP framework includes standard interfaces and enables direct updates to hardware procedures without requiring a new flash code or a firmware patch.

A three-dimensional (3D) integrated circuit (IC) device can include a first die having a first supply line and a second die having a second supply line, a power header, and a voltage selection logic. The power header can be connected to the first die and the second die and configured to generate a first voltage on a first voltage line and a second voltage on a second voltage line. The voltage selection logic can be connected to the first supply line and the second supply line and configured to select between the first voltage line and the second voltage line for each of the first supply line and the second supply line.

Reconfigurable power distribution system for three-dimensional integrated circuits

A memory controller may receive a plurality of thermal profiles from a plurality of three-dimensional (3D)-stacked memory chips, where the plurality of thermal profiles include thermal profile data for the memory chips, where the thermal profile data includes a memory chip usage data and a location data for each of the memory chips, and where the memory chips include a first memory chip and a second memory chip. The memory controller may generate a first predicted memory chip usage data and location data by analyzing the usage data and location data of the thermal profile data. A second predicted memory chip usage data and location data may be generated. Based on the predicted memory chip, fractional memory chip read propensity data may be generated. The memory controller may distribute, according the first fractional memory chip read propensity distribution, memory chip read operations.

Read distribution in a three-dimensional stacked memory based on thermal profiles

A method, system, and computer program product for system-wide power conservation using memory cache are provided. A memory access request is received at a location in a memory architecture where processing the memory access request has to use a last level of cache before reaching a memory device holding a requested data. Using a memory controller, the memory access request is caused to wait, omitting adding the memory access request to a queue of existing memory access requests accepted for processing using the last level of cache. All the existing memory access requests in the queue are processed using the last level of cache. The last level of cache is purged to the memory device. The memory access request is processed using an alternative path to the memory device that avoids the last level of cache. A cache device used as the last level of cache is powered down.

System-wide power conservation using memory cache

A system provides complex branch execution hardware and a hardware-based Multiplexer (MUX) to multiplex a fetch address of a future branch and a preloaded branch fetch address to create an index hash value that is used to index a branch target prediction table for execution by a processor core, in order to reduce branch mis-prediction by preloading.

Branch target preloading using a multiplexer and hash circuit to reduce incorrect branch predictions

A memory controller is equipped with multiple error correction circuits for different complexity levels of errors, but requested data is initially sent to a requesting unit (e.g., processor) via a bypass path which provides the lowest memory latency. The requesting unit performs error detection and, if an error is found, sends a retry select signal to the memory controller. The retry select signal provides an indication of which error correction unit should be used to provide complete correction of the error but add the minimum latency necessary. On the retry transmission, the controller uses the particular error correction unit indicated by the retry select signal. The memory controller can also have a persistent error detection circuit which identifies an address as being defective when an error is repeatedly indicated by multiple retry select signals, and the control logic can automatically transmits the requested data using the appropriate error correction unit.

ECC bypass using low latency CE correction with retry select signal

A system for memory device control may include a stacked memory device and a memory controller. The stacked memory device may include a stack of chips connected to a package substrate by electrical interconnects. The stack may include a plurality of memory chips, a primary control chip, and a secondary control chip. The primary and secondary control chips may be electrically connected to the plurality of memory chips by an internal data bus. The primary control chip may have logic to provide an interface between the internal data bus and a first external data bus. The secondary control chip may have logic to provide an interface between the internal data bus and a second external data bus.

Stacked memory device control

Data is retrieved from a stacked memory device having a plurality of slave memory chips in response to recognizing a problem in the stacked memory device. The problem is determined to be associated with a primary driver module in the stacked memory device. In response, the primary driver module is disabled and an emergency driver module is enabled. Each of the plurality of slave memory chips are selected using a multiplexing unit to retrieve data using the emergency driver module.

Data retrieval from stacked computer memory

A method for mirroring in three-dimensional-stacked memory includes receiving a plurality of thermal profiles from a plurality of memory chips. The method also includes ranking the plurality of memory chips in a first ranked list of memory chips as a function of the plurality of thermal profiles and forming a first group of memory chips from the plurality of memory chips based on the first ranked list of memory chips. The method also includes forming a second group of memory chips from the plurality of memory chips distinct from the first group of memory chips based on the first ranked list of memory chips. The method also includes pairing a first memory chip from the first group of memory chips and a second memory chip from the second group of memory chips, and mirroring the pairing of memory chips.

Mirroring in three-dimensional stacked memory

Growing community of inventors

Austin, TX, United States of America

Kenneth Lee Wright