Credence Systems Corporation

Kenneth L Skala

Gregory Illes

Richard B Morris

Duane A Champoux

Jeffrey D Currin

James Michael Jula

Vicki L Skala, Legal Representative

An efficient automated test system and method are presented. In one embodiment, an automated test system is implemented in a routed event distribution architecture. In one exemplary implementation, an automated test system includes a plurality of test instruments, a switched event bus, and a test controller component. The plurality of test instruments perform testing. The switched event bus communicatively couples the plurality of instruments. The switched event bus comprises an event distribution switch that flexibly routes event information across event lines of the switched event bus. The test controller controls the testing and the switched event bus.

Routed event test system and method

An integrated circuit (IC) tester includes a set of nodes providing test access to separate terminals of an IC and each carrying out a sequence of actions at the terminal in response to test vector sequences. Each node includes a low speed vector memory supplying test vectors during the test. A host writes vectors into the vector memories before the test sending them over a common bus to vector write caches within each node. The write caches compensate for access speed limitations of the vector memory. During the test, blocks of vectors are read out of the vector memory at a low rate and written into a high speed read cache array. An instruction processor within each node reads individual vectors read out of the read cache array at a high rate and uses them for controlling test operations at the node during each cycle of the test. The read cache array not only compensates for the low speed vector memory, it also allows the instruction processor to re-use repeated vector patterns, thereby reducing the number of vectors that must be distributed to the nodes.

Integrated circuit tester with cached vector memories

An integrated circuit (IC) tester includes a master controller and a set of tester nodes. Each tester node includes a vector memory controller, a vector memory, and a pin electronics circuit. During a test the pin electronics circuit carries out the sequence of actions in response to a sequence of vectors produced by the vector memory controller. To prepare for a test, a separate set of vectors is written into each vector memory. The vector memory controller thereafter moves blocks of vectors from the vector memory as needed to an internal vector cache. During the test, the master controller sends the same sequence of instructions concurrently to each vector memory controller. Each vector memory controller executes each instruction of the sequence by generating and supplying an address to the vector cache. The vector cache responds by reading out an addressed test vector and supplying it to the pin electronics circuit. Some instructions instruct the vector memory controllers to generate repeating patterns of vector cache addresses so that the read caches produce repeating patterns of output vectors. This enables the tester to perform repetitive portions of a test without drawing additional vectors from the vector memories, thereby reducing the number of vectors that must be distributed thereto.

Integrated circuit tester with distributed instruction processing

An integrated circuit (IC) tester employs both central and distributed data sources for controlling tester operation during a test. The tester includes a master controller, a central scan data source, and a set of tester nodes. Each tester node carries out a sequence of test actions at an IC terminal, each action being defined by a data word (test vector). Before the test sets of vectors are written into vector memories in the nodes and separate control data is loaded into registers in each node. During the test, the scan data source sends scan data words concurrently to all tester nodes, and each node stores them. The master controller sends a similar instruction to each tester node during each cycle of the test. Some instructions reference a vector stored in the node and instruct all tester nodes to carry out the action indicated by the referenced vector. Other instructions tell the tester nodes to alter a last read vector by replacing selected bits of the referenced vector with selected bits of a stored scan data word and then to carry out an action indicated by the altered vector. The control data tells each tester node which bits of the vector (if any) to replace and which bits of the scan data word are used as replacements. The scan data controls node operations during portions of a test when only a few nodes are actively changing their activities at their IC terminals from cycle to cycle.

Dual source data distribution system for integrated circuit tester

An integrated circuit tester includes a node for each terminal of a device under test. Each node includes a pin electronics circuit for carrying out test activities at the device terminal and a vector memory system for supplying a vector sequence to the local pin electronics circuit for controlling its test activities. To program the tester, a host computer transmits an appropriate set of vectors to each vector memory system via a common bus. Before sending vectors to the vector memory systems, the host computer sends them control data assigning each to one or more 'virtual channels' such that all vector memory systems that are to receive a similar set of vectors are assigned to a similar virtual channel. Also, before transmitting each set of vectors on the bus, the host computer broadcasts additional control data to all vector memory systems designating one virtual channel as active. Thereafter only those vector memory systems assigned to the active virtual channel accept the transmitted vector set. Thus the host computer can concurrently write the same set of vectors to more than one vector memory system when the pin electronics circuits they control are to carry out similar test activities.

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Fremont, CA, United States of America

Kenneth L Skala