Taiwan Semiconductor Manufacturing Comp. Ltd.

Kenneth L Ho

Danping Peng

Junjiang Lei

Daniel Beylkin

Sagar Vinodbhai Trivedi

Fangbo Xu

Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.

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San Francisco, CA, United States of America

Kenneth L Ho