Unisys Corporation

Sperry Corporation

Kenneth L Engelbrecht

John Steven Kuslak

David C Johnson

Douglas A Fuller

Kenneth E Merryman

Kevin C Cleereman

Lawrence R Fontaine

Joseph P Kerzman

Hans Christian Mikkelsen

James Edward Rezek

Wayne D Ward

Gary J Lucas

Archie E Lahti

Robert J Palermo

Gerald G Fagerness

Ronald G Arnold

Conrad S Shimada

Gregory Allen Marlan

Nguyen T Tran

Donald R Kalvestrand

A system and method are provided for detecting and recovering from errors in an Instruction Cache RAM and/or Operand Cache RAM of an electronic data processing system. In some cases, errors in the Instruction Cache RAM and/or Operand Cache RAM are detected and recovered from without any required interaction of an operating system of the data processing system. Thus, and in many cases, errors in the Instruction Cache RAM and/or Operand Cache RAM can be handled seamlessly and efficiently, without requiring a specialized operating system routine, or in some cases, a maintenance technician, to help diagnose and/or fix the error.

System and method for detecting and recovering from errors in an instruction stream of an electronic data processing system

A system and method are provided for detecting and recovering from errors in a control store memory of an electronic data processing system. In some cases, errors in the control store memory are detected and recovered from without any required interaction with an operating system of the data processing system. Thus, errors in the control store memory can be handled seamlessly and efficiently, without requiring a maintenance technician, or in some cases, a specialized operating system routine, to help diagnose and fix the error.

System and method for detecting and recovering from errors in a control store of an electronic data processing system

A system and method for increasing processing performance in a computer system by asynchronously performing system activities that do not conflict with normal instruction processing, during inactive memory access periods. The computer system includes at least one instruction processor to process instructions of an instruction stream, and a memory to store data. One or more inactive data blocks in the memory are identified, and a list of addresses corresponding to the identified inactive data blocks is generated. Available computing cycles occurring during processing in the computer system are identified, such as processing stalls and idle memory write periods. The inactive data blocks associated with the list of addresses are initialized to a predetermined state, during the available computing cycles. Addresses corresponding to those initialized data blocks are then made available to the computing system to facilitate use of the data blocks.

Method and apparatus for increasing computer performance through asynchronous memory block initialization

A method and apparatus for using an optimization tool to optimize a design that uses a gated clock structure. In short, the present invention allows a standard optimizer tool to determine the relative timing of two or more signals that arrive at a logic gate, wherein the logic gate forms a gated clock signal. Typically, standard optimizer tools can only check the relative timing between two or more signals that arrive at a storage element. In accordance with the present invention, selected logic gates may be modeled as a storage element. Thus, a standard optimizer tool may be used to correctly optimize a design that uses a gated clock structure, and in particular, to correctly optimize the logic that provides the clock and enable signals to a clock gating element.

Method and apparatus for optimizing a gated clock structure using a

A method and apparatus for optimizing a circuit design having multi-cycle paths therein. In an exemplary embodiment, a circuit design having a number of multi-cycle paths may be optimized by: identifying at least one of the number of multi-cycle paths within the circuit design, and identifying the corresponding qualified clocks associated therewith; replacing selected ones of the corresponding clocks with replacement clocks; and optimizing the circuit design using the replacement clocks. By using a replacement clock that has a clock period equal to the corresponding clock, which is typically a qualified clock, a standard optimization tool may correctly optimize the circuit design.

Method and apparatus for optimizing a circuit design having multi-paths

An apparatus for and method of providing a data processing system that delays the writing of an architectural state change value to a corresponding architectural state register for a predetermined period of time. This may provide the instruction processor with enough time to determine if the architectural state change is valid before the architectural state change is actually written to the appropriate architectural state register.

Delayed state writes for an instruction processor

Method and apparatus for changing the sequential execution of instructions in a pipelined instruction processor by using a microcode controlled redirect controller. The execution of a redirect instruction by the pipelined instruction processor provides a number of microcode bits including a target address to the redirect controller, a predetermined combination of the microcode bits then causes the redirect controller to redirect the execution sequence of the instructions from the next sequential instruction to a target instruction.

Instruction flow control for an instruction processor

A method and apparatus for identifying gated clocks within a circuit design. In a typical design, each of the number of gated clock signals is uniquely determined by a particular logical combination of a number of raw clock signals and a number of enable signals. In the present invention, the gated clock signals may be identified by: identifying which of the number of raw clock signals is coupled, through combinational logic, to a selected one of the number of state devices, thereby resulting in an identified raw clock signal; identifying which of the number of enable signals is coupled, through combinational logic, to the selected one of the number of state devices, thereby resulting in an identified enable signal; and determining which of the number of gated clock signals is uniquely determined by the particular combination of the identified raw clock signal and the identified enable signal.

Method and apparatus for identifying gated clocks within a circuit

Method and apparatus for performing microcode paging during instruction execution in an instruction processor. In a preferred embodiment an instruction processor is provided that includes both a microcode ROM and a microcode RAM. The microcode ROM stores the current release of the microcode for the computer system, and the microcode RAM stores microcode patch instructions. During instruction execution, the present invention selects between the output of the microcode ROM and the microcode RAM, depending on whether the instruction requires a patch microcode instruction. If the desired microcode patch instruction is not stored in the microcode RAM, the instruction processor is temporarily interrupted and the desired microcode patch instruction or a group of microcode patch instructions are written, or paged, into the microcode RAM.

Method and apparatus for performing microcode paging during instruction

A method and apparatus for efficiently optimizing a circuit design by substituting identified cells within the circuit design with logically equivalent cells having different drive strengths. The present invention eliminates the need to update the design database and to place and route the circuit design during each design iteration. Rather, an improved extraction tool is provided which incorporates a cell substitution list, and updates the RC file therefrom. The updated RC file is used by the timing analysis tool to determine if the updated design will meet the design specification. After the design meets the design specification, a final place and route may be performed.

Method and apparatus for performing drive strength adjust optimization

A system for overlapping macro instruction execution is described for use in a data processing system. A pair of control storage devices each store the micro instruction sets required to execute all macro instructions in the repertoire and are used for alternate macro instructions. Each of the controlled storage devices is addressable to entry addresses by the macro instructions. After entry, addressing is by the contents of the micro instructions with provision made for conditional branching. An overlap count storage device is provided for storing overlap counts for all possible sequences of macro instructions. These overlap counts define the number of micro instructions of the current macro instruction that must be executed before the next macro instruction can proceed. Micro instruction execution is by clock cycle and are counted as they are executed. The count is compared to the stored overlap count for the current sequence of macro instructions and overlap execution is enabled when comparison is found. Overlap of macro instruction execution is allowed to occur when the current remaining micro instructions for the current macro instruction define functions that are mutually exclusive with the functions controlled by the next macro instruction. During overlap, micro instructions are loaded in an execution register from both control storage devices. Overlapping instructions that have variable execution sequences is controlled by halting the count of micro instruction executions until the variable sequence has been completed.

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Blaine, MN, United States of America

Kenneth L Engelbrecht