Hewlett-packard Company

Tandem Computers Incorporated

Kenneth K Chan

James B Williams

William R Bryg

John F Shelton

Michael L Ziegler

Robert D Odineal

Thomas R Hotchkiss

Robert E Naas

Thomas B Alexander

Ehsan Rashid

Craig R Frink

Eric R Delano

Yie-Fong Dan

Geoffrey I Iswandhi

Martin W Sanner

Robert J Brooks

Wing M Chan

Edward M Jacobs

Brendan A Voge

James E Korpi

John L Wood

Jay A Zwagerman

Duc Manh Hoang

Julie W Moncton

Julie W Wu

Steven G Silverman

Zubair Hussain

David L Bernick

James E Smith

A double cache snoop mechanism in uniprocessor computer systems having a cache and coherent I/O and multiprocessor computer systems reduces the number of cycles that a processor is stalled during a coherency check. The snoop mechanism splits each coherency check, such that a read-only check is first sent to the cache subsystem., and a read-write check is sent thereafter only if there is a cache hit during the read-only check, and there is the need to modify the cache. Average processor pipeline stall time is reduced even though a cache hit results in an additional coherency check because most coherency checks do not result in a cache hit.

Method and apparatus for checking cache coherency in a computer

An apparatus and method for duplicating tag addresses to maintain addresses of central processing unit (CPU) data stored in write buffers external to a cache are disclosed. Advance notification of write transactions is issued to allow a subsystem that maintains duplicate cache tags to know in advance which write transactions are present in the CPU's buffers. Such information is used to keep duplicate tags for both the cache and any buffers that contain writes that are to be removed from the cache. The cache is preferably a direct mapped cache and the CPU preferably resides within a multiprocessor architecture. In the preferred embodiment, all write transactions are indirectly caused by a read transaction that is about to bring a line into the cache. Thus, a read transaction is issued by the CPU before the write transaction is issued. A field is added to the read transaction that indicates whether or not the read transaction has a corresponding line that must be written out of the cache and into a buffer, such that the duplicate tags duplicate both the CPU cache and the CPU write buffers.

Method and apparatus for duplicating tag systems to maintain addresses

A data communication system for communicating data between a bus running at a first clock frequency and a circuit block operating synchronously with the data bus at a second clock frequency. The system includes a clock generator for generating a bus clock signal at the first clock frequency and a chip clock signal at the second clock frequency wherein the first and second clock signal frequencies are in the ratio of (N-1):N where N is an integer greater than 1 and wherein the bus and chip clock signals are synchronized once every N cycles of the chip clock signal. The clock generator also generates a synchronization signal indicating the chip clock signal cycle in which the bus and chip clock signals are synchronized. The circuit block includes an interface circuit for receiving and transmitting data on the bus. The system also includes circuits connected to each circuit block for identifying a chip clock signal cycle in which data cannot be transmitted by the circuit block on the bus and a chip clock signal cycle in which data cannot be received by the circuit block from the bus, there being one of each type of cycle in each contiguous block of N chip clock cycles.

Apparatus and method for operating chips synchronously at speeds

Clock generating means for generating bus clock and chip clock

A coherency scheme of use with a system having a bus, a main memory, a main memory controller for accessing main memory in response to transactions received on the bus, and a set of processor modules coupled to the bus. Each processor module has a cache memory and is capable of transmitting coherent transactions on the bus to other processor modules and to the main memory controller. Each processor module detects coherent transactions issued on the bus and performs cache coherency checks for each of the coherent transactions. Each processor module has a coherency queue for storing all transactions issued on the bus and for performing coherency checks for the transactions in first-in, first-out order. When a module transmits a coherent transaction on a bus, it places its own transaction into its own coherency queue.

Multiprocessor system for maintaining cache coherency by checking the

A computer system has a multi-tiered bus system. The multi-tiered bus system includes one or more local buses and a central bus connected to each local bus by a bus interface. In order to maintain one global view of transaction ordering, the processors on each local bus record bus transactions in an order on which the bus transactions appear on the central bus. To do this, bus transactions which are initiated on any local bus are forwarded to the central bus by the corresponding bus interface. The processors connected to the local bus do not record bus transactions when they are initiated on the local bus. Every transaction which occurs on the central bus is echoed back to every local bus by the corresponding bus interface. Each processor records bus transactions at the time they are echoed back to the local bus.

Coherent transaction ordering in multi-tiered bus system

A bus system having a bus arbitration scheme. The bus system includes a bus and a plurality of client modules coupled to the bus. Each of the client modules is capable of transmitting information on the bus to another of client module, and only one client module is entitled to transmit information on the bus at any time. A module entitled to transmit information on the bus has control of the bus for a minimum period of time defining a cycle. To determine which module is entitled to use the bus, each client module generates an arbitration signal when it seeks to transmit information on the bus. Each client module has an arbitration signal processor responsive to the arbitration signals for determining whether the module is entitled to transmit information on said bus. The system preferably also contains a host module that informs the client modules what types of transactions allowed on the bus in a given cycle. Each arbitration signal processor preferably is also responsive to the client option signals sent by the host module during an earlier cycle.

Fast pipelined distributed arbitration scheme

The present invention provides a protocol method for waiting the bus in a digital computer and an apparatus for implementing that protocol. By allowing the bus to continue running after a wait command has been asserted, modules on the computer bus are not required to respond instantly to the wait command. Information on the bus during the multiple cycles of the wait period is defined as invalid and valid data is driven on the bus after the wait period has expired. Bus driver modules are provided with a replay queue to replay, on the bus, data the driver module drove on the bus during the wait period if required.

Wait state mechanism for a high speed bus which allows the bus to

In a digital computer system which employs a plurality of host processors, at least two system buses and a plurality of peripheral input/output ports, an input/output system is provided whereby ownership of the input/output channels is shared. The device controller employs a first port controller having a first ownership latch, a second port controller having a second ownership latch, a first bus, a dedicated microprocessor having control over the first bus (the MPU bus), a second, higher-speed bus, a multiple-channel direct memory access (DMA) controller which is a state machine which controls the second bus (the data buffer bus), a bus switch for exchanging data between buses, a multiple device peripheral device interface, namely a Small Computer System Interface (SCSI), and at least provision for interface with data communication equipment (DCEs) or data terminal equipment (DTEs). The DMA controller arbitrates data bus usage and can allocate alternate bus clock cycles in response to requests to exchange data and is capable of supporting overlapping transfers. The microprocessor is allowed access to the data buffer bus only if the data buffer bus is not in use for data transfer. The latches associated with each port grant ownership to either port or both ports allowing data exchange between addressed peripheral devices and requesting ports.

Input/output system for multiprocessors

Growing community of inventors

San Jose, CA, United States of America

Kenneth K Chan