Globalfoundries U.S. Inc.

International Business Machines Corporation

Globalfoundries Inc.

Kenneth John Giewont

Yusheng Bian

Karen A Nummy

Roderick Alan Augur

Neena Garg

Michal Rakowski

Junedong Lee

Kevin K Dezfulian

Devendra K Sadana

Anthony Gene Domenicucci

Stephen Richard Fox

Bo Peng

Ajey Poovannummoottil Jacob

Steven M Shank

Kwong Hon Wong

Theodore James Letavic

Andreas Daniel Stricker

Dan Moy

Maurice Heathcote Norcott

Russell Herbert Arndt

Won Suk Lee

Scott R Stiffler

Siegfried Lutz Maurer

Asif J Chowdhury

Jeffery Burton Maxson

Anthony J Yu

Craig M Ransom

Petar I Todorov

Aurelia A Suwarno-Handayana

Shamas M Ummer

Yun Yu Wang

Charles W Koburger, Iii

Cyril Cabral, Jr

Kirk David Peterson

Dominic Joseph Schepis

Subramanian Srikanteswara Iyer

Siva P Adusumilli

Yun-Yu Wang

Paul Christian Parries

Michael John Hargrove

Edward William Kiewra

Jerome Brett Lasky

Luke G England

Jessie Carrigan Rosenberg

Ryan W Sporer

Gerd Pfeiffer

Eric Adler

Horatio Seymour Wildman

M Dean Sciacca

Peter Stevens Locke

Marc Waine Cantell

Thomas F Houghton

Stephen Bruce Brodsky

Keith Donegan

Richard J Murphy

Abu Thomas

Venkata Narayana Rao Vanukuru

James Patrick Norum

Shuren Hu

Michael Joseph MacDonald

Takako Hirokawa

Kevin E Mello

Asli Sahin

David B Riggs

Isabel Ying Yang

Thomas Houghton

Frank J Schmidt, Jr

Judith A Coffin

Prateek Kumar Sharma

Lawrence Bauer, Jr

Bosang Kim

Jeffrey Lloyd

Kent Way

Terrance M Tornatore

Gregory D Pomarico

Michael E Adamcek

Thomas R Kupiec

Brian E Johnson

IC chips for photonics applications are disclosed. An example IC chip includes a substrate, an optical component above the substrate, and a first connection level above the substrate. The first connection level includes the optical component and a first cladding structure, in which the optical component is covered by the first cladding structure. The IC chip also includes a second connection level on the first connection level. The second connection level includes a first interlayer dielectric material. The IC chip further includes a second cladding structure directly above the optical component. The second cladding structure has at least a section within the second connection level. The second cladding structure is on the first cladding structure. The second cladding structure is laterally adjacent to and in direct contact with the first interlayer dielectric material. The second cladding structure includes a material different from the first interlayer dielectric material.

Cladding structure in the back end of line of photonics chips

Structures for a waveguide escalator and methods of forming such structures. A structure comprises a first waveguide core, and a back-end-of-line stack including a first dielectric layer, a second dielectric layer on the first dielectric layer, an opening in the second dielectric layer, a second waveguide core including a section that overlaps with a section of the first waveguide core, and a plurality of third waveguide cores disposed between the section of the first waveguide core and the section of the second waveguide core. The plurality of third waveguide cores are positioned inside the opening in the second dielectric layer, the first dielectric layer comprises a first material with a first refractive index, and the second dielectric layer comprises a second material with a second refractive index different from the first refractive index.

Waveguide escalators for a photonics chip

Structures including an inductor and methods of forming such structures. The structure comprises a semiconductor substrate including a first plurality of sealed cavities and a back-end-of-line stack on the semiconductor substrate. Each sealed cavity includes an air gap, and the back-end-of-line stack includes an inductor having a winding that overlaps with the scaled cavities.

Inductors with airgap electrical isolation

Disclosed is a photonic integrated circuit (PIC) structure including a first waveguide core with a first end portion, a second waveguide core with a second end portion overlaying and physically separated from the first end portion, and a coupler configured to facilitate low-loss optical signal transmission between the waveguide cores. The coupler can include at least one array of photonic material elements (e.g., photonic crystal elements or photonic metamaterial elements) embedded in cladding material between the end portions. Alternatively, the coupler can include at least one photonic material layer (e.g., a photonic crystal layer or a photonic metamaterial layer) between and physically separated from the end portions and an array of cladding material elements extending through the photonic material layer. Also disclosed is a PIC structure including an on-chip system (e.g., a photonic computing system) including a crossing array implemented using any of the above-described couplers.

Photonic integrated circuit structure with coupler for interlayer waveguide coupling

Structures for an edge coupler and methods of forming a structure for an edge coupler. The structure includes a waveguide core over a dielectric layer, and a back-end-of-line stack over the waveguide core and the dielectric layer. The back-end-of-line stack includes an interlayer dielectric layer, a side edge, a first feature, a second feature, and a third feature laterally arranged between the first feature and the second feature. The first feature, the second feature, and the third feature are positioned on the interlayer dielectric layer adjacent to the side edge, and the third feature has an overlapping relationship with a tapered section of the waveguide core.

Metamaterial edge couplers in the back-end-of-line stack of a photonics chip

A laser structure, including: a dielectric matrix formed of a first material; a laser source formed within the dielectric matrix and formed of a semiconductor material; and a plurality of side confining features formed within the dielectric matrix and extending parallel to and along a length of the laser source. The plurality of side confining features are formed of the semiconductor material.

Confining features for mode shaping of lasers and coupling with silicon photonic components

Disclosed is a photonic structure and associated method. The structure includes a closed-curve waveguide having a first height, as measured from the top surface of an insulator layer, and an outer curved sidewall that extends essentially vertically the full first height (e.g., to minimize signal loss). The structure includes a closed-curve thermal coupler and a heating element. The closed-curve thermal coupler is thermally coupled to and laterally surrounded by the closed-curve waveguide and has a second height that is less than the first height. In some embodiments, the closed-curve waveguide and the closed-curve thermal coupler are continuous portions of the same semiconductor layer having different thicknesses. The heating element is thermally coupled to the closed-curve thermal coupler and thereby indirectly thermally coupled to the closed-curve waveguide. Thus, the heating element is usable for thermally tuning the closed-curve waveguide via the closed-curve thermal coupler to minimize any temperature-dependent resonance shift (TDRS).

Optical device with low-loss thermally tunable closed-curve optical waveguide

Structures including an edge coupler and methods of forming a structure including an edge coupler. The structure includes a waveguide core over a dielectric layer and a back-end-of-line stack over the dielectric layer and the waveguide core. The back-end-of-line stack includes a side edge and a truncated layer that is overlapped with a tapered section of the waveguide core. The truncated layer has a first end surface adjacent to the side edge and a second end surface above the tapered section of the waveguide core. The truncated layer is tapered from the first end surface to the second end surface.

Edge couplers in the back-end-of-line stack of a photonics chip

Structures for an edge coupler and methods of fabricating a structure for an edge coupler. A first waveguide core has a first section that has a tapered shape and a second section that is adjoined to the first section. Multiple segments are positioned with a spaced arrangement adjacent to an end surface of the second section of the first waveguide core. A slab layer is adjoined to the first section of the first waveguide core. A second waveguide core has a section that overlaps with the first section of the first waveguide core to define a layer stack. The section of the second waveguide core has a tapered shape, and the first and second waveguide cores are comprised of different materials. The first section of the first waveguide core has a first thickness, and the slab layer has a second thickness that is less than the first thickness.

Hybrid edge couplers with stacked inverse tapers

Structures including an edge coupler and methods of fabricating a structure including an edge coupler. The structure includes a dielectric layer including an edge, a waveguide core region on the dielectric layer, and multiple segments on the dielectric layer. The waveguide core region has an end surface, and the waveguide core region is lengthwise tapered toward the end surface. The segments are positioned between the waveguide core region and the edge of the dielectric layer. A waveguide core has a section positioned over the waveguide core region in an overlapping arrangement. The waveguide core has an end surface, and the section of the waveguide core is lengthwise tapered toward the end surface.

Hybrid edge couplers with layers in multiple levels

A photonics integrated circuit includes a semiconductor substrate; a buried insulator layer positioned over the semiconductor substrate; and a back-end-of-line (BEOL) insulator stack over a first portion of the buried insulator layer. In addition, the PIC includes a silicon nitride (SiN) waveguide edge coupler positioned in a first region over the buried insulator layer and at least partially under the BEOL insulator stack. An oxide layer extends over a side of the BEOL insulator stack. The SiN waveguide edge coupler provides better power handling and fabrication tolerance than silicon waveguide edge couplers, despite the location under various BEOL layers. The PIC can also include silicon waveguide edger coupler(s).

Photonics integrated circuit with silicon nitride waveguide edge coupler

Structures including a grating coupler and methods of fabricating a structure including a grating coupler. The structure includes structure includes a dielectric layer on a substrate, a first waveguide core positioned in a first level over the dielectric layer, and a second waveguide core positioned in a second level over the dielectric layer. The second level differs in elevation above the dielectric layer from the first level. The first waveguide core includes a tapered section. The structure further includes a grating coupler having a plurality of segments positioned in the second level adjacent to the second waveguide core. The segments of the grating coupler and the tapered section of the first waveguide core are positioned in an overlapping arrangement.

Optical components in the back-end-of-line stack of a photonics chip using plural cores vertically stacked

Growing community of inventors

Hopewell Junction, NY, United States of America

Kenneth John Giewont