International Business Machines Corporation

Other

Freescale Semiconductor,inc.

Chartered Semiconductor Manufacturing Ltd (corporation)

Infineon Technologies North America Corp.

Kenneth Jay Stein

Richard Paul Volant

Kevin Shawn Petrarca

John Michael Cotte

Seshadri Subbanna

Donald Francis Canaperi

Robert Allen Groves

Mahadevaiyer Krishnan

Anil Kumar Chinthakindi

Hariklia Deligianni

Panayotis Constantinou Andricacos

John Harold Magerlein

Joseph Thomas Kocis

Douglas Duane Coolbaugh

Ebenezer E Eshun

Gary Robert Hueckel

Daniel C Edelstein

Xiangdong Chen

David Louis Harame

Dae-Gyu Park

Kwong Hon Wong

Gregory Gower Freeman

Nancy Anne Greco

Kunal Vaed

David Angell

Dominique Nguyen Ngoc

Ping-Chuan Wang

Timothy Joseph Dalton

Christopher Vincent Jahnes

Chandrasekharan Kothandaraman

Edmund Juris Sprogis

Kathryn Turner Schonenberg

Voon-Yew Thean

Deok-Kee Kim

John Matthew Safran

Dan Moy

Basanth Jagannathan

Norman Whitelaw Robson

Jennifer L Lund

Shwu-Jen Jeng

William C Wille

Donna Rizzone Cote

James Anthony Tornello

Melanie J Sherony

Weipeng Li

L Paivikki Buchwalter

Jeffrey R Amadon

John C Bisson

Anthony K Stamper

Effendi Leobandung

Theodorus E Standaert

Vijay Narayanan

Terence B Hook

Haizhou Yin

Zhong-Xiang He

Timothy Dooling Sullivan

Jeffrey Bowman Johnson

Paul Stephen Andry

Bucknell Chapman Webb

Herbert Lei Ho

Robert Mark Rassel

Laertis Economikos

Min Yang

Huajie Chen

Michael F Lofaro

William J Cote

Joseph Francis Shepard, Jr

Michael D Armacost

Jin-Ping Han

Hongwen Yan

Yong Meng Lee

Peter James Lindgren

Da Zhang

Ephrem G Gebreselasie

Anda C Mocuta

Young-Hee Kim

Andreas Augustin

Cornelia Kang-I Tsang

Anita Madan

Young Way Teh

Laegu Kang

Fen Fen Jamin

David C Ahlgren

John Chester Malinowski

Thomas A Wallner

Christopher M Schnabel

Gerald R Friese

Helen Wang

John E Heidenreich, Iii

Jay M Shah

David M Rockwell

Chendong Zhu

Ys Suh

Franck Arnaud

Jong Ho Lee

Scott A Seymour

K T Schonenberg

Paivikki Buchwalter

James Tornello

Panayotis Andricacos

Methods of fabricating replacement metal gate transistors using bi-layer a hardmask are disclosed. By utilizing a bi-layer hardmask comprised of a first layer of nitride, followed by a second layer of oxide, the topography issues caused by transition regions of gates are mitigated, which simplifies downstream processing steps and improves yield.

Replacement metal gate transistors using bi-layer hardmask

A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including: a high-K dielectric region; a blocking region disposed against at least one surface of the high-K dielectric region and adapted to form an oxidized layer in response to exposure to oxygen; and an oxygen rich region disposed against the blocking region such that the blocking region is interposed between the oxygen rich region and the high-K dielectric region.

Self-limiting oxygen seal for high-K dielectric and design structure

A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.

Metal gate integration structure and method including metal fuse, anti-fuse and/or resistor

An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.

Balancing NFET and PFET performance using straining layers

An epitaxial layer of silicon (Si) or silicon-germanium (SiGe) extends over the edge of silicon trench isolation (STI), thereby increasing the effective width of an active silicon region (RX) bordered by the STI. The RX region may have a &#x3c;100&#x3e; crystal orientation. An effective width of an FET device formed in the RX region may be increased, therefore performance may be improved with same density. Isolation may not be degraded since RX-to-RX distance is same at bottom. Junction capacitance may be reduced since part of the RX is on STI.

Method to increase effective MOSFET width

A metal layer and a semiconductor layer are sequentially deposited on a substrate. The semiconductor layer and the metal layer are lithographically patterned to form a stack of a semiconductor portion and a metal gate portion, which is preferably performed concurrently with formation of at least one metal gate stack. In one embodiment, the size of the semiconductor portion is reduced and a metal semiconductor alloy portion is formed on the semiconductor portion by metallization. In a first electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the metal semiconductor alloy portion and the metal gate portion. In another embodiment, two disjoined metal semiconductor alloy portions are formed on the semiconductor portion. In a second electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the two previously disjoined metal semiconductor alloy portions.

Metal gate compatible electrical antifuse

A through substrate via includes an annular conductor layer at a periphery of a through substrate aperture, and a plug layer surrounded by the annular conductor layer. A method for fabricating the through substrate via includes forming a blind aperture within a substrate and successively forming and subsequently planarizing within the blind aperture a conformal conductor layer that does not fill the aperture and plug layer that does fill the aperture. The backside of the substrate may then be planarized to expose at least the planarized conformal conductor layer.

Through substrate annular via including plug filler

Disclosed are embodiments of a p-type, silicon germanium (SiGe), high-k dielectric-metal gate, metal oxide semiconductor field effect transistor (PFET) having an optimal threshold voltage (Vt), a complementary metal oxide semiconductor (CMOS) device that includes the PFET and methods of forming both the PFET alone and the CMOS device. The embodiments incorporate negatively charged ions (e.g., fluorine (F), chlorine (Cl), bromine (Br), iodine (I), etc.) into the high-k gate dielectric material of the PFET only so as to selectively adjust the negative Vt of the PFET (i.e., so as to reduce the negative Vt of the PFET).

Method to reduce threshold voltage (Vt) in silicon germanium (SiGe), high-k dielectric-metal gate, p-type metal oxide semiconductor field effect transistors

A method of forming an inductor. The method including: (a) forming a dielectric layer on a top surface of a substrate; after (a), (b) forming a lower trench in the dielectric layer; after (b), (c) forming a resist layer on a top surface of the dielectric layer; after (c), (d) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and after (d), (e) completely filling the lower trench and at least partially filling the upper trench with a conductor in order to form the inductor.

Method of fabricating a high Q factor integrated circuit inductor

A through-wafer via structure and method for forming the same. The through-wafer via structure includes a wafer having an opening and a top wafer surface. The top wafer surface defines a first reference direction perpendicular to the top wafer surface. The through-wafer via structure further includes a through-wafer via in the opening. The through-wafer via has a shape of a rectangular plate. A height of the through-wafer via in the first reference direction essentially equals a thickness of the wafer in the first reference direction. A length of the through-wafer via in a second reference direction is at least ten times greater than a width of the through-wafer via in a third reference direction. The first, second, and third reference directions are perpendicular to each other.

Through-wafer vias

A method of forming an inductor. The method includes: forming a dielectric layer on a substrate; forming a lower trench in the dielectric layer; forming a liner in the lower trench and on the dielectric layer; forming a Cu seed layer over the liner; forming a resist layer on the Cu seed layer; forming an upper trench in the resist layer; electroplating Cu to completely fill the lower trench and at least partially fill the upper trench; removing the resist layer; selectively forming a passivation layer on all exposed Cu surfaces; selectively removing the Cu seed layer from regions of the liner; and removing the thus exposed regions of the liner from the dielectric layer, wherein a top surface of the inductor extends above a top surface of the dielectric layer, the passivation layer remaining on regions of sidewalls of the inductor above the top surface of the dielectric layer.

A semiconductor micro-electromechanical system (MEMS) switch provided with noble metal contacts that act as an oxygen barrier to copper electrodes is described. The MEMS switch is fully integrated into a CMOS semiconductor fabrication line. The integration techniques, materials and processes are fully compatible with copper chip metallization processes and are typically, a low cost and a low temperature process (below 400&#xb0; C.). The MEMS switch includes: a movable beam within a cavity, the movable beam being anchored to a wall of the cavity at one or both ends of the beam; a first electrode embedded in the movable beam; and a second electrode embedded in an wall of the cavity and facing the first electrode, wherein the first and second electrodes are respectively capped by the noble metal contact.

Method of forming noble metal contacts

Methods of forming a high dielectric constant dielectric layer are disclosed including providing a process chamber including a holder for supporting a substrate, introducing a first gas comprising a high dielectric constant (Hi-K) dielectric precursor and an oxygen (O) oxidant into the process chamber to form a first portion of the high dielectric constant dielectric layer on the substrate, and switching from a flow of the first gas to a flow of a second gas comprising the Hi-K dielectric precursor and an ozone (O) oxidant to form a second portion of the high dielectric constant dielectric layer on the first portion. In an alternative embodiment, another portion can be formed on the second portion using the oxygen oxidant. The invention increases throughput by at least 20% without reliability or leakage degradation and without the need for additional equipment.

Hi-K dielectric layer deposition methods

Noble metal contacts for micro-electromechanical switches

An integrated circuit includes a bilayer thin film resistor in which the lower layer is a seed layer that controls the crystal structure of the upper layer. The thickness of the lower layer and the thickness of the upper layer may be chosen to form a resistor with a TCR having a design value.

Thin film resistors of different materials

Growing community of inventors

Sandy Hook, CT, United States of America

Kenneth Jay Stein