Advanced Micro Devices Corporation

Kenneth James Kotlowski

Brett A Tischler

Willard S Briggs

Daniel Daugherty

Systems and methods for cache-based compressed display data storage are provided. One system includes memory operable to store compressed display data, a processor comprising a processing core and a cache, a cache storage module operably coupled to the memory and the processor, wherein the cache storage module is to initiate a storage of at least a portion of the compressed display data in the cache in response to an indication that the processing core is in an inactive mode. One method comprises, in response to an indication that a processor is in an inactive mode, transferring compressed display data from a frame buffer in memory to a cache associated with the processor, obtaining a first compressed display data from the cache, and decompressing the first compressed display data to generate a first uncompressed display data.

System and method for cache-based compressed display data storage

Video control signals are received at a video input port of a system. A determination is made whether the video control signals are valid or invalid. When video control signals represent a valid video signal, providing a delayed representation of a control signal to a synchronization input of a display engine of the system, and when the video control signals represent an invalid video signal, providing a an alternative signal to the synchronization input of the display engine.

Method and apparatus of providing video synchronization

There is disclosed a bus interface unit for transferring machine specific register (MSR) requests between a plurality of bus devices. The bus interface unit comprises: 1) a plurality of input ports for receiving incoming MSR requests from the plurality of bus devices; 2) a plurality of output ports for transmitting data to the plurality of bus devices; and 3) a controller for reading N routing associated with a first received MSR request and comparing a first identification (ID) value in a predetermined M-bit field in the N routing bits to a first designated value. The controller, in response to a determination that the first ID value does not equal the first designated value: 1) realigns the N routing bits such that remaining ones of the N-M bits outside the predetermined M-bit field are moved into the predetermined M-bit field and 2) transmits the realigned N routing bits via a first one of the plurality of output ports identified by the first ID value.

System and method for machine specific register addressing in external devices

A master unit and a slave unit in a data processor are coupled together by a data bus. The master unit sends data transactions to the slave unit through the data bus and the slave unit executes the data transactions. The present invention comprises an apparatus and method for executing a data transaction either (1) by executing the data transaction 'in order' with respect to other data transactions received by the slave unit, or (2) by executing the data transaction 'out of order' with respect to other data transactions received by the slave unit. The master unit assigns a priority identifier to each data transaction. The slave unit reads the priority identifier to determine whether to execute the data transaction &#x201c;in order&#x201d; or &#x201c;out of order&#x201d; with respect to the other data transactions.

Apparatus and method for sending in order data and out of order data on a data bus

There is disclosed a bus interface unit for transferring data between a plurality of bus devices. The bus interface unit comprises: 1) a first bus device interface comprising: a) a first incoming request bus for receiving request packets from a first one of the plurality of bus devices; b) a first outgoing request bus for transmitting request packets to the first bus device; c) a first incoming data bus for receiving data packets from the first bus device; and d) a first outgoing data bus for transmitting data packets to the first bus device; and 2) a second bus device interface comprising: a) a second incoming request bus for receiving request packets from a second one of the plurality of bus devices; b) a second outgoing request bus for transmitting request packets to the second bus device; c) a second incoming data bus for receiving data packets from the second bus device; and d) a second outgoing data bus for transmitting data packets to the second bus device.

Split transactional unidirectional bus architecture and method of operation

In a method and system for transferring data between a plurality of bus devices, a bus interface unit includes a first bus device interface (FBDI), a second bus device interface (SBDI), and an arbitration circuit. Each of the FBDI and SBDI includes a corresponding incoming and outgoing request bus for receiving and transmitting request packets from a corresponding one of the plurality of bus devices. Similarly, each of the EBDI and SBDI also includes a corresponding incoming and outgoing data bus for receiving and transmitting data packets from the corresponding one of the plurality of bus devices. The arbitration circuit is capable of determining priority level associated with corresponding request packets received from the FBDI and the SBDI respectively.

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Berthoud, CO, United States of America

Kenneth James Kotlowski