Xilinx, Inc.

Kenneth J Stickney, Jr

Raymond Kong

Jeffrey V Lindholm

Nicolas J Camilleri

Edward S McGettigan

Richard J LeBlanc

Premduth Vidyanandan

Jennifer D Baldwin

Philippe Garrault

Kevin L Bixler

Carrie L Kisiday

A process is provided for creating an input/output (I/O) model. A set of logical I/O pins of an unplaced and unrouted circuit design is determined. Pin placement is determined for one or more of the logical I/O pins on device pins of a target device. An I/O pin profile for each of the logical I/O pins is determined. A plurality of I/O pin models available on the target device are input and an I/O pin model is selected from the plurality of I/O pin models for each of the logical I/O pins according to the respective I/O pin profiles. An I/O model is generated including each selected I/O pin model within the I/O model. The generated I/O model is stored in a processor readable storage medium.

Generation of input/output models

A clock template includes digital programming information for programming clock frames of a programmable gate array (PGA). The digital programming information represents a number of different clock configurations that correspond to various designs in the PGA. In one embodiment, the digital programming information includes a bit stream for partially reconfiguring the PGA. In another embodiment, the digital programming information is embedded in digital programming information of at least one of the designs. Methods of configuring a PGA with different designs having different clocking configurations by utilizing the clock template are also disclosed.

Clock template for configuring a programmable gate array

Growing community of inventors

Boulder, CO, United States of America

Kenneth J Stickney, Jr