Other

International Business Machines Corporation

Kenneth J Shaw

Steven Frederick Oakland

Kavin Asavanant

Hayden C Cranford, Jr

Frank David Ferraiolo

Ilya I Novof

Carrie Ellen Cox

Roland A Bechade

Gary Stephen Ditlow

Leon Skarshinski

Dac C Pham

Marc R Turcotte

Bruce Kaufmann

A method of and system for purchasing an item using contributions from multiple people enables multiple users to contribute towards a gift. Typically the gift is one that each user would not purchase individually, but as a group, each user is able to contribute a portion of the total payment. Preferably, a gift host selects the gift, provides desired information and invited contributors are informed of the gift by email. The invited contributors then provide the necessary information to contribute before a deadline is reached. If the contributions are enough to purchase the gift, the gift is purchased and is given to a gift receiver.

Method of and system for purchasing an item using contributions from multiple people

An (SST) driver circuit having additional circuitry for minimizing data-dependent jitter in the SST driver and increasing frequency amplitude in the SST driver. The additional circuity comprises a plurality of switches configured to be turned on or pulsed on momentarily during operation to discharge a node in the SST output stage for the purpose of removing the stored charge before the next transition cycle of the output stage.

Nodal charge compensation for SST driver having data mux in output stage

A programmable logic array (PLA) is provided with a decoder at the input. Each product term line of the PLA has an associated power switch that is controlled by an output of the decoder. Only a portion of the PLA that includes the product term lines activated for a particular operation is powered up for that operation, thus minimizing power consumption.

Low power, high performance PLA

A process independent digital clock signal timing network is described for generating a chip clock substantially in phase with and offset by one cycle from an input clock signal. The timing network determines the delay experienced by a clock signal passing through a predetermined internal clock circuit on the chip and pregates the internal clock circuit by an amount equivalent to the determined delay such that the chip clock signal output from the internal clock circuitry lags the external clock signal input to the semiconductor chip by one cycle. Various timing network embodiments are described and claimed.

Clock signal latency elimination network

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Essex Junction, VT, United States of America

Kenneth J Shaw