International Business Machines Corporation

Globalfoundries Inc.

Kenneth J Reyer

Donald W Plass

James W Dawson

Gregory J Fredeman

Paul Alan Bunce

Thomas J Knips

Abraham Mathews

John D Davis

Dinesh Kannambadi

John Edward Barth, Jr

Thomas E Miller

Bishan He

A method includes receiving, at a bitline-mux driver circuit, a subarray activation (SUBA) signal and a delay signal. The bitline-mux driver circuit includes a header circuit operable to output a driver voltage to a plurality of driver circuits. The driver voltage is boosted through a voltage divider with diode header circuit based on the SUBA signal to set the driver voltage to a value above a standard supply voltage (VDD) and between a voltage bitline high (VBLH) level and a high voltage (VPP) level. The VPP level exceeds a maximum allowed voltage (VMAX) level of the driver circuits. A master wordline output of the driver circuits is driven to select a bitline mux of a computer memory module based on an address input signal, the delay signal, and the driver voltage.

Bit-line mux driver with diode header for computer memory

Techniques for voltage bitline high (VBLH) regulation for a computer memory are described herein. An aspect includes generating, by a resistor ladder and a diode compensation footer, a VBLH reference signal based on a high voltage (VPP) in a computer memory module. Another aspect includes regulating a VBLH signal based on the VBLH reference signal. Another aspect includes regulating a wordline driver voltage of the computer memory module based on the VBLH signal.

Voltage bitline high (VBLH) regulation for computer memory

A driver circuit and associated techniques include managing voltage driving an electronic device. An input signal having a first voltage level is received. Processes may perform level shifting of the first voltage level to a second voltage level. The second voltage level may be clamped, for instance, but a diode circuit. The second output voltage level may be programmable, as may be current and resistance levels of the driver circuit.

Dynamic high voltage driver with adjustable clamped output level

A single-ended input sense amplifier uses a pass device to couple the input local bit-line to a global bit-line evaluation node. The sense amplifier also includes a pair of cross-coupled inverters, a first inverter of which has an input that coupled directly to the global bit-line evaluation node. The output of the second inverter is selectively coupled to the global bit-line evaluation node in response to a control signal, so that when the pass device is active, the local bit line charges or discharges the global bit-line evaluation node without being affected substantially by a state of the output of the second inverter. When the control signal is in the other state, the cross-coupled inverter forms a latch. An internal output control circuit of the second inverter interrupts the feedback provided by the second inverter in response to the control signal.

Gated-feedback sense amplifier for single-ended local bit-line memories

A method of operation of a high-voltage word-line driver circuit for a memory device prevents any single transistor of the driver from having the full power supply voltage from which the word-line output signal is generated, from being applied across any single transistor of the word-line driver circuit. A pair of cascode devices are connected in series with the pull-down device of the input stage and a pull-up device of the input stage, and biased using reference voltages to control the maximum voltage drop across the pull-down device when the pull-down device is off and the pull-up device is active, and to control the maximum voltage drop across the pull-up device when the pull-down device is active. The output stage also includes cascode devices that protect the output pull-down and pull-up devices, and the reference voltages that bias the input and output cascode pairs may be the same reference voltages.

Dynamic cascode-managed high-voltage word-line driver circuit

A high-voltage word-line driver circuit for a memory device uses cascode devices to prevent any single transistor of the driver circuit from having the full power supply voltage from which the word-line output signal is generated, from being applied across any single transistor of the word-line driver circuit. A pair of cascode devices are connected in series with the pull-down device of the input stage and a pull-up device of the input stage, and biased using reference voltages to control the maximum voltage drop across the pull-down device when the pull-down device is off and the pull-up device is active, and to control the maximum voltage drop across the pull-up device when the pull-down device is active. The output stage also includes cascode devices that protect the output pull-down and pull-up devices, and the reference voltages that bias the input and output cascode pairs may be the same reference voltages.

Write control circuitry and control method are provided for a memory array configured with multiple memory subarrays. The write control circuitry includes multiple subarray write controllers associated with the multiple memory subarrays, each subarray write controller selectively enabling a local write control signal to its associated memory subarray. The selectively enabling is responsive to a received subarray select signal, wherein only one subarray select signal is active at a time. At least some subarray write controllers are powered at least in part via a switched power node, wherein powering of the switched power node is distributively implemented among the subarray write controllers. In one example, the distributively implemented powering of the switched power node is accomplished via multiple inverters distributed among the subarray write controllers, each inverter having an output coupled to the switched power node, and an input coupled to receive a global write enable signal.

Write control method for a memory array configured with multiple memory subarrays

Write control circuitry and method for a memory array configured with multiple memory subarrays

A method and apparatus for implementing ABIST data compression and serialization for memory built-in self test of SRAM with redundancy. The method includes providing detection signals asserted for one failing data out, two failing data outs, and greater than two failing data outs. The method also includes individually encoding the failing bit position of each corresponding failing data out with a binary representation value corresponding therewith. The method further includes serializing results of the providing detection signals and the individually encoding, and transmitting results of the serializing to a redundancy support register function on a single fail buss.

ABIST data compression and serialization for memory built-in self test of SRAM with redundancy

A clock control method and apparatus are provided employing a clock control circuit which generates an array clock for a memory array from a system clock and a reset control signal. The reset control signal is one of a plurality of input control signals to the clock control circuit. When the system clock is below a predefined frequency threshold, the reset control signal is an array tracking reset signal, wherein the active pulse width of the array clock is system clock frequency independent, and when the system clock is above the predefined frequency threshold, the reset control signal is a mid-cycle reset signal, meaning that the active pulse width of the array clock is system clock frequency dependent. A bypass signal is provided as a third input control signal, which when active causes the clock control circuit to output an array clock which mirrors the system clock.

Clock control method and apparatus for a memory array

A decoder circuit includes a pulse powered stage having a plurality of fan-in inputs thereto, a dynamic stage fed by the pulse powered stage, and a replica node selectively coupled to an output node of the pulse powered stage by a pass device. The pass device and the dynamic stage are controlled by a clock signal so as to enable a self-timed evaluation of the pulse-powered stage with a clocked enablement of the dynamic stage.

Fast pulse powered NOR decode apparatus for semiconductor devices

A decoder circuit includes a pulse powered stage having a plurality of fan-in inputs thereto, a dynamic stage fed by the pulse powered stage, and a replica node selectively coupled to an output node of the pulse powered stage by a pass device. The pass device and the dynamic stage are controlled by a clock signal so as to enable a self-timed evaluation of the pulse-powered stage with a clocked enablement of the dynamic stage. A pull up device restores the dynamic stage to a precharged condition, the pull up device controlled by a second clock signal independent of the first clock signal.

Fast pulse powered NOR decode apparatus with pulse stretching and redundancy steering

A bitline selection apparatus for a semiconductor memory device includes a first local bitline pair and a second local bitline pair selectively coupled to a global bitline pair, each of the first and second local bitline pairs including a true bitline and a complementary bitline. Each of the true bitlines is selectively coupled to a common true node through an n-type pass device and a p-type pass device in parallel therewith, and each of the complementary bitlines is selectively coupled to a common complementary node through an n-type pass device and a p-type pass device in parallel therewith.

High density bitline selection apparatus for semiconductor memory devices

A memory redundancy control apparatus includes a static compare stage configured to compare bits of a requested memory address to corresponding fuse information bits representing a defective memory address. A dynamic stage is configured to receive outputs of the static compare stage, with an output of the dynamic stage being precharged so as to initially deactivate primary subarray decoding circuitry. The dynamic stage is further triggered by a clock signal thereto. Upon activation of the clock signal, the output of the dynamic stage remains precharged whenever a match exists between the requested memory address and the defective memory address, and the output of the dynamic stage is discharged whenever a mismatch exists between the requested memory address and the defective memory address. A delay tracking clock generator is configured to generate a delay tracking clock signal with respect to the dynamic stage, to gate the output of the dynamic stage to spare subarray decoding circuitry, wherein the spare subarray decoding circuitry is activated whenever the output of the dynamic stage remains precharged following activation of the clock signal.

Growing community of inventors

Stormville, NY, United States of America

Kenneth J Reyer