Enhanced Memory Systems, Inc.

Purple Mountain Server LLC

United Memories, Inc.

Nippon Steel Semiconductor Corporation

Zettacore, Inc.

Other

Ramtron International Corporation

Ramtron Corporation

International Business Machines Corporation

The Ohio State University

Inmos Limited

Nmb Semiconductor Company, Ltd.

Kenneth J Mobley

Oscar Frederick Jones, Jr

Ronald H Sartore

Donald G Carrigan

David W Bondurant

Michael Peters

Kim Carver Hardee

Ritu Shrivastava

Michael W Schuette

Antonio R Gallo

Bruce Grieshaber

David Fisch

Tom DeBolske

Michael T Peters

Werner G Kuhr

Steven William Tomashot

S Sheffield Eaton, Jr

Richard L McCreery

Jim L Rogers

Michael Alwais

Jing Wu

Steve W Ash

Molecular memories, i.e., memories that incorporate molecules for charge storage, are disclosed. Molecular memory cells, molecular memory arrays, and electronic devices including molecular memory are also disclosed, as are processing systems and methods for manufacturing molecular memories. Methods of manufacturing molecular memories that enable semiconductor devices and interconnections to be manufactured monolithically with molecular memory are also disclosed.

Processing systems and methods for molecular memory

The electronic properties of molecular junctions of the general type carbon/molecule/TiO/Au as examples of 'molecular heterojunctions' consisting of a molecular monolayer and a semiconducting oxide. Junctions containing fluorene bonded to pyrolyzed photoresist film (PPF) were compared to those containing AlOinstead of fluorene, and those with only the TiOlayer. The responses to voltage sweep and pulse stimulation were strongly dependent on junction composition and temperature. A transient current response lasting a few milliseconds results from injection and trapping of electrons in the TiOlayer, and occurred in all three junction types studied. Conduction in PPF/TiO/Au junctions is consistent with space charge limited conduction at low voltage, then a sharp increase in current once the space charge fills all the traps. With fluorene present, there is a slower, persistent change in junction conductance which may be removed by a reverse polarity pulse. This 'memory' effect is attributed to a redox process in the TiOwhich generates Tiand/or Ti, which have much higher conductance than TiOdue to the presence of conduction band electrons. The redox process amounts to &#x201c;dynamic doping&#x201d; of the TiOlayer by imposed electric field. The memory effect arises from a combination of the properties of the molecular and oxide layers, and is a special property of the molecular heterojunction configuration.

Electronic junction devices featuring redox electrodes

A method and device for hiding refresh operations during accesses to sub-arrays of a pseudo-static memory device. By refreshing sub-arraywhile filling the row R(where i&#x2260;j) corresponding to sub-array, refresh operations can be performed without risking that a read request will interrupt the refresh operation. Additional refresh operations of sub-arraycan be performed serially with the operations of filling the row Rwithout delaying the overall burst read or write operation if the burst is made sufficiently long.

Method for hiding a refresh in a pseudo-static memory

A memory and method for operating it provide for increased data access speed. In an implementation, a synchronous memory or SDRAM includes a central memory region with memory blocks arranged in sets on respective opposite sides. A number of primary sense amplifier sets are provided, each set being associated with a respective set of the memory blocks and located adjacent. A row cache is provided in the central memory region, and row decoders decode a row address in response to a 'bank activate' command and move data from a decoded row address into a primary sense amplifier set associated with a memory block containing the decoded row address and into the row cache, before application of a 'read' command to the SDRAM. Column decoders decode a column address in response to a &#x201c;read&#x201d; command and for reading data from the cache in accordance with the decoded column address.

Method and circuit for increasing the memory access speed of an enhanced synchronous memory

Method for hiding a refresh in a pseudo-static memory with plural DRAM sub-arrays and an on-board address decoder

An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address. Asynchronous operation of the DRAM is achieved by decoupling the row registers from the DRAM array, thus allowing the DRAM cells to be precharged or refreshed during a read of the row register.

Enhanced DRAM with embedded registers

An SDRAM and method for operating it provide for increased data access speed. The SDRAM includes a central memory region with memory blocks arranged in sets on respective opposite sides. A plurality of primary sense amplifier sets are provided, each set being associated with a respective set of the memory blocks and located adjacent thereto. A row cache is provided in the central memory region, and row decoders decode a row address in response to a &ldquo;bank activate&rdquo; command and move data from a decoded row address into a primary sense amplifier set associated with a memory block containing the decoded row address and into the row cache, prior to application of a &ldquo;read&rdquo; command to the SDRAM. Column decoders decode a column address in response to a &ldquo;read&rdquo; command and for reading data from the cache in accordance with the decoded column address.

Method and circuit for increasing the memory access speed of an enhanced synchronous SDRAM

A memory architecture uses shared sense amplifiers ( ) and a centralized cache ( ) that contains M bits. The memory architecture also includes a global bus ( ) connecting the sense amplifiers and the centralized cache. The global bus includes n bits, and n<M bits are transferred in M/n cycles to the centralized cache.

Method for reducing the width of a global data bus in a memory architecture

A method and system for hiding DRAM cycle time behind burst read and write accesses. A combined read and write data transfer area interacts with a set of sense amplifiers to accelerate read and write cycles. By independently isolating the read data transfer areas and the write data transfer areas, data can be transferred (1) from the DRAM array to the read data transfer areas, (2) from the write data transfer areas to the DRAM array, and (3) from the write data transfer areas to the read data transfer areas.

Structure and method for hiding DRAM cycle time behind a burst access

A double data rate (&ldquo;DDR&rdquo;) synchronous dynamic random access memory (&ldquo;SDRAM&rdquo;) device incorporating a static random access memory (&ldquo;SRAM&rdquo;) cache per memory bank that provides effectively double peak data bandwidth, optimizes sustained bandwidth and improves bus efficiency as compared with conventional DDR SDRAM devices. The memory device disclosed provides effectively faster basic DRAM memory latency parameters, faster page &ldquo;hit&rdquo; latency, faster page &ldquo;miss&rdquo; latency and sustained bandwidth on random burst reads, faster read-to-write latency and write-to-read latency, hidden precharge, hidden bank activate latency, hidden refresh and hidden write precharge during a read &ldquo;hit&rdquo;.

Double data rate synchronous dynamic random access memory device incorporating a static RAM cache per memory bank

An enhanced bus turnaround integrated circuit dynamic random access memory (&ldquo;DRAM&rdquo;) device of particular utility in providing maximum DRAM performance while concomitantly affording a device with may be readily integrated into systems designed to use zero bus turnaround (&ldquo;ZBT&rdquo;), or pipeline burst static random access memory (&ldquo;SRAM&rdquo;) devices. The enhanced bus turnaround DRAM device of the present invention provides much of the same benefits of a conventional ZBT SRAM device with a similar pin-out, timing and function set while also providing improvements in device density, power consumption and cost approaching that of straight DRAM memory. Through the provision of a &ldquo;Wait&rdquo; pin, the enhanced bus turnaround device of the present invention can signal the system memory controller when additional wait states must be added yet still provide virtually identical data access time performance to that of ZBT SRAM for all Read and Write operations with a burst length of four or greater. Use of master/slave and inhibit pins.

Enhanced bus turnaround integrated circuit dynamic random access memory device

A cached synchronous dynamic random access memory (cached SDRAM) device having a multi-bank architecture and a programmable caching policy includes a synchronous dynamic random access memory (SDRAM) bank, a synchronous static randomly addressable row register, a select logic gating circuit, and mode register for programming of the cached SDRAM to operate in a Write Transfer mode corresponding to a Normal Operation mode of a standard SDRAM during a Write cycle, and to operate in a No Write Transfer mode according to an alternate operation mode during a Write cycle, thereby operating under a first and a second caching policy, respectively. The SDRAM includes a row decoder for selecting a row of data in a memory bank array, sense amplifiers for latching the row of data selected by the row decoder, and a synchronous column selector for selecting a desired column of the row of data. The row register stores a row of data latched by the sense amplifiers and the select logic gating circuit, disposed between the sense amplifiers and the row register, selectively gates the row of data present on the bit lines to the row register in accordance to particular synchronous memory operations being performed.

Cached synchronous DRAM architecture having a mode register programmable cache policy

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Colorado Springs, CO, United States of America

Kenneth J Mobley