Motorola Corporation

Kenneth J Long

James H Carlquist

Thomas R Yarbrough

Edward C Dasse

Kelvin L Holub

Marcus R Burton

Alfredo Figueroa

Walid S Ballouli

Charles F Toewe

Robert W Bollish

Shih K Cheng

Bobby W Formby

Wafer level testing of a wafer (500) is accomplished by dividing the integrated circuits of the wafer into a plurality of segmented bus regions (514, 516, and 518 for example). Each bus region is formed having its own set of test conductors (520-530) wherein each set of test conductors are isolated from all other sets of test conductors on the wafer. Each test conductor has at least one contact pad (531-546) where each contact pad lies within a periphery of the integrated circuits' active areas. By forming pads over ICs and by sub-dividing the bus structure of test conductive lines, more high powered ICs can be tested in a wafer-level manner with fewer problems associated with speed, power, throughput, and routing problems.

Apparatus for performing wafer-level testing of integrated circuits

A semiconductor wafer (20) having integrated circuit dice (22), wafer conductors (42-47, 50-53), and wafer contact pads (38) formed thereon. The wafer conductors (42-47, 50-53) are used to transfer electrical signals to and from the integrated circuit dice (22) on semiconductor wafer (20) so that wafer level testing and burn-in can be performed on the integrated circuit dice (22). In accordance with one embodiment of the present, each wafer conductor (45, 52) is electrically coupled to the same bonding pad (78) on each integrated circuit dice (22). Each wafer conductor (42-47, 50-53) includes at least a portion of conductor (42-47) which overlies the upper surface of at least one integrated circuit dice (22).

Apparatus for performing wafer level testing of integrated circuit dice

Method and apparatus for performing wafer level testing of integrated

A method for handling semiconductor components by utilizing a removable filler strip for temporarily securing or clinching longitudinally arrangeable individual components in a tube, rod or hollow magazine. The filler strip is generally flat, but has surface features that serve to press the components against the top, bottom or side of the tube. Partial removal of the filler strip will result in the dispensing of some of the components while the remainder are retained by the filler strip in the tube.

Method for handling semiconductor components

A filler strip for temporarily securing or clinching longitudinally arrangeable individual components in a tube, rod or hollow magazine. The filler strip is generally flat, but has surface features that serve to press the component against the top, bottom or side of the tube to prevent the component from knocking against adjacent components and cracking, chipping or otherwise damaging one or more of the components. The filler strip is particularly suited to eliminating the knocking motion of expensive ceramic integrated circuit packages that are shipped and handled in transparent plastic tubes or rails.

Filler strips

Growing community of inventors

Austin, TX, United States of America

Kenneth J Long