3com Corporation

Kenneth J DeLong

David S Miller

Edward A Heiner, Jr

Benny Siman-Tov

Jihad Boura

Gary Dudley

A switching system connectable to a communications network and configured to handle logical multicast data without degrading the flow of other data through the system. The switching system includes a plurality of input ports, a plurality of output ports, and a plurality of queues for buffering streams of data units being routed through the system. The switching system further includes at least one meter for metering data units to ensure that the data units conform to predetermined Quality of Service criteria. The logical multicast data is metered once at the meter and subsequently replicated and transmitted onto the communications network a predetermined number of times at an output port so as not to degrade the flow of other data through the system.

Logical multicast packet handling

A cache line index for an address cache entry is calculated by organizing an address such as a Media Access Control (&ldquo;MAC&rdquo;) address into a plurality of intermediate elements, barrel shifting the bits of at least one of the intermediate elements in accordance with predetermined criteria, and folding the intermediate address elements together with an exclusive-OR function. A Virtual Local Area Network (&ldquo;VLAN&rdquo;) index may also be included in cache line index calculation. The VLAN index enables segmentation of the cache into virtual tables. The tag portion of the cache entry includes a subset of the complete set of intermediate elements. The intermediate elements in the cache entry can be employed in conjunction with the cache line index to recover the original MAC address. Hence, the size of the tag portion of the address cache entry is reduced relative to the full MAC address without a reduction in the information content of the entry.

Hash equation for MAC addresses that supports cache entry tagging and virtual address tables

A distributed data structure providing an indication of the validity of a data value or values associated with a given key value. The data structure has at least one data entry associated with each of plural key entries. The validity indication enables asynchronous updates to key and data entries by preventing retrieval of invalid data values, while enabling a simultaneous search of the key entries for a particular key value. The validity indication also allows the data structure to be sparsely populated; it is possible to mark a key value as invalid such that binary searching of the data structure is unaffected and invalid data is not retrieved. Data structure throughput is enhanced as a result of minimized maintenance overhead.

Method and apparatus using a binary search engine for searching and maintaining a distributed data structure

In a network switch with a distributed address cache, events that update a cache segment are serialized and distributed and acted upon by all the cache segments to maintain consistency among the segments. The segments are individually associated with Input/Output Application Specific Integrated Circuits ('I/O ASICs') interconnected via an event sharing bus used for transmission of cache update messages. Messages are ordered by arbitrating for the shared bus and enforcing that an I/O ASIC does not update its local cache segment until a cache update message is broadcast on the event bus. Each I/O ASIC asserts a busy signal while executing a cache update message to prevent an arbiter from granting the event bus to allow transmission of a subsequent update message; thereby synchronizing all update messages and minimizing storage on each I/O ASIC for update messages. A weakly coherent mechanism predicated on the observation that address learning operations and address aging operations are self correcting is employed which permits cache update messages to be flushed when cache line conflicts are detected.

Coherence mechanism for distributed address cache in a network switch

An arbiter circuit is employed to isolate a processor from a plurality of Input/Output Application Specific Integrated Circuits ('I/O ASICs'). The processor is coupled to the arbiter through a control bus, an address bus and a data bus. The arbiter is coupled to the I/O ASICs through an extension of the control bus and a combined address/data bus. The arbiter manages control of the control bus extension and address/data bus to enable contemporaneous transmission ('broadcast') of messages to the I/O ASICs, and enable the processor to access the I/O ASICs. Only one of the I/O ASICs is granted control of the control bus extension and address/data bus at any point in time. The processor may also be granted sole control of the control bus extension and address/data bus.

Growing community of inventors

Hollis, NH, United States of America

Kenneth J DeLong