Everspin Technologies, Inc.

Freescale Semiconductor,inc.

Other

Kenneth H Smith

Sanjeev Aggarwal

Nicholas David Rizzo

Brian R Butcher

Jon Michael Slaughter

Renu Whig

Phillip G Mather

Kerry Joseph Nagel

Gregory W Grynkewich

Clarence J Tracy

Kelly Wayne Kyler

Moazzem Hossain

Mark A Durlam

Richard Williams

Charles A Synder

Srinivas V Pietambaram

Bradley Neal Engel

James R Wasson

Pawitter Jit Mangat

Anthony Ciancio

Philip Mather

Joe Mogab

A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a 'Z' axis magnetic field onto sensors orientated in the XY plane.

Methods of manufacturing a magnetic field sensor

A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.

Method of integration of a magnetoresistive structure

A method of manufacturing one or more interconnects to a magnetoresistive structure, the method comprising depositing a first conductive material (i) in a via which is formed through a first surface of a first dielectric layer and (ii) directly on the first surface of the first dielectric layer. The method further includes etching the first conductive material wherein, after etching the first conductive material, a portion of the first conductive material remains (i) in the via and (ii) directly on the first surface of the first dielectric layer. The method also includes partially filling the via by depositing a second conductive material (i) in the via and (ii) directly on the first conductive material remaining in the via, depositing a first electrode material (i) in the via and (ii) directly on the second conductive material which is in the via, and forming a magnetoresistive structure over the first electrode material.

A conductive via disposed beneath a magnetic device and aligned therewith. In certain embodiments, an electrode formed on the conductive via may be polished to eliminate step functions or seams originating at the conductive via from propagating up through the various deposited layers. This integration approach allows for improved scaling of the MRAM devices to, for example, a 45 nanometer node.

Process integration of a single chip three axis magnetic field sensor

A conductive via for connecting between a digit line and one side of the magnetic device is positioned beneath, and aligned with, each magnetic device. Other contacts may satisfy the same design rules, using the same process step. An electrode formed on the conductive via is polished to eliminate step functions or seams originating at the conductive via from propagating up through the various deposited layers. This integration approach allows for improved scaling of the MRAM devices to at least a 45 nanometer node, a cell packing factor approaching 6F, and a uniform thickness of material between the bit lines and the underlying memory elements.

Magnetic random access memory integration having improved scaling

A method of forming a magnetoelectronic device includes forming a dielectric material () surrounding a magnetic bit (), etching the dielectric material () to define an opening () over the magnetic bit () without exposing the magnetic bit (), the opening () having a sidewall, depositing a blanket layer () of cladding material over the dielectric material (), including over the sidewall, removing by a sputtering process the blanket layer () in the bottom of the opening () and the dielectric material () over the magnetic bit (), and forming a conductive material () within the opening () to form a bit line (). This process reduces errors caused by process irregularities such as edges of the bits () protruding and thereby causing defects in the cladding layer () formed thereover. A bit line or digit line so formed may optionally be tapered at the ends () to prevent magnetic reversal of the bit line magnetic moment that otherwise may occur due to external magnetic fields.

Structure and method for fabricating cladded conductive lines in magnetic memories

Growing community of inventors

Chandler, AZ, United States of America

Kenneth H Smith