Cisco Technology, Inc.

Cisco Systems Inc.

Kenneth H Potter

John William Marshall

Trevor Garner

William Robert Lee

Darren R Kerr

Barry Scott Burns

Robert E Jeter, Jr

Stephen Charles Hilla

Hong-Man Wu

Gary S Muntz

Michael L Wright

Guy Fedorkow

Christopher J Kappler

Jonathan Rosen

Ramesh Sivakolundu

Jeffery B Scott

John Mitten

Scott Nellenbach

Robert Leroy King

William P Brandt

Russell E Schroter

Christopher James Lefelhocz

Manish Changela

Maruthingendra P Rachepalli

Robert T Olsen

Guy C Fedorkow

Russell Schroter

Techniques for distributing data packets over a network link bundle include storing an output data packet in a data flow queue based on a flow identification associated with the output data packet. The flow identification indicates a set of one or more data packets, including the output data packet, which are to be sent in the same sequence as received. State data is also received. The state data indicates a physical status of a first port of multiple active egress ports that are connected to a corresponding bundle of communication links with one particular network device. A particular data flow queue is determined based at least in part on the state data. A next data packet is directed from the particular data flow queue to a second port of the active egress ports. These techniques allow a more efficient use of a network link bundle.

Method and apparatus for dynamic load balancing over a network link bundle

An inter-chip communication (ICC) mechanism enables any processor in a pipelined arrayed processing engine to communicate directly with any other processor of the engine over a low-latency communication path. The ICC mechanism includes a unidirectional control plane path that is separate from a data plane path of the engine and that accommodates control information flow among the processors. The mechanism thus enables inter-processor communication without sending messages over the data plane communication path extending through processors of each pipeline.

Inter-chip processor control plane communication

A technique efficiently accesses locks associated with resources in a computer system. A processor accesses (e.g., acquires or releases) a lock by specifying and issuing a request to a resource controller, the request containing attribute and resource location information associated with the lock. In response, the resource controller applies the information contained in the request to an outstanding lock data structure to determine if the request should be blocked, blocked as a pending writer, allowed or an error condition. If the request is blocked, it remains blocked until the outstanding lock blocking the request is released. If the request is allowed, operations associated with the request are performed.

Zero overhead resource locks with attributes

An aggregation router architecture comprises a plurality of line cards coupled to at least one performance routing engine (PRE) via an interconnect system. The line cards include input cards having input ports coupled to subscribers and at least one trunk card configured to aggregate packets received from the subscriber inputs over at least one output port. The PRE performs packet forwarding and routing operations, along with quality of service functions for the packets received from each input line card over the interconnect system. The interconnect system comprises a plurality of high-speed unidirectional (i.e., point-to-point) links coupling the PRE to each line card. The point-to-point links couple the line cards to a novel logic circuit of the PRE that is configured to interface the line cards to a packet buffer and a forwarding engine of the PRE.

High performance interface logic architecture of an intermediate network node

A technique for controlling access to resources that may be accessed by one or more entities in a system. According to the technique, an entity accesses a shared resource by issuing a request containing an identifier that identifies the resource and an operation that specifies an operation to be performed on the resource. The operation is compared with one or more outstanding operations associated with the shared resource to determine if the operation conflicts with one or more of the outstanding operations. If a conflict is detected, a guard value is applied to determine if a race condition could occur. If a race condition is detected, the operation is blocked; otherwise, the operation is allowed.

Memory controller that tracks queue operations to detect race conditions

The present invention comprises a technique for performing a reassembly assist function that enables a processor to perform packet reassembly in a deterministic manner. The technique employed by the present invention enables a processor to reassemble a packet without having to extend its normal processing time to reassemble a varying number of fragments into a packet. The invention takes advantage of the fact that the reassembly assist can be dedicated exclusively to reassembling a packet from a series of fragments and thereby offloading the reassembly process from the processor.

Multi-link protocol reassembly assist in a parallel 1-D systolic array system

The present invention provides a system and method for a plurality of independent processors to simultaneously assemble requests in a context memory coupled to a coprocessor. A write manager coupled to the context memory organizes segments received from multiple processors to form requests for the coprocessor. Each received segment indicates a location in the context memory, such as an indexed memory block, where the segment should be stored. Illustratively, the write manager parses the received segments to their appropriate blocks of the context memory, and detects when the last segment for a request has been received. The last segment may be identified according to a predetermined address bit, e.g. an upper order bit, that is set. When the write manager receives the last segment for a request, the write manager (1) finishes assembling the request in a block of the context memory, (2) enqueues an index associated with the memory block in an index FIFO, and (3) sets a valid bit associated with memory block. By setting the valid bit, the write manager prevents newly received segments from overwriting the assembled request that has not yet been forwarded to the coprocessor. When an index reaches the head of the index FIFO, a request is dequeued from the indexed block of the context memory and forwarded to the coprocessor.

Multi processor enqueue packet circuit

A load balancing mechanism and technique that monitors a memory interface associated with a processor resource in a processor pool associated with at least one node of a computer network. The monitoring determines the actual load activity executed by the processor during a specified period of time. The mechanism comprises a hardware access monitor configured to determine the true activity of each processor resource. The access monitor tracks certain memory requests over the memory interface and stores the requests in a counter assigned to each processor. The access monitor then collects statistics from each processor resource of the pool and provides those statistics to a central load balancing resource for use when determining assignment of loads (tasks) to the various processor resources.

System and method for process load balancing in a multi-processor environment

The present invention provides a technique for ordering responses received over a split transaction bus, such as a HyperTransport bus (HPT). When multiple non-posted requests are sequentially issued over the split transaction bus, control logic is used to assign each request an identifying (ID) number, e.g. up to a maximum number of outstanding requests. Similarly, each response received over the split transaction bus is assigned the same ID number as its corresponding request. Accordingly, a 'response memory' comprises a unique memory block for every possible ID number, and the control logic directs a received response to its corresponding memory block. The responses are extracted from blocks of response memory in accordance with a predetermined set of ordering rules. For example, the responses may be accessed in the same order the corresponding non-posted requests were issued.

Split transaction reordering circuit

A mapping technique allows a forwarding engine of an intermediate node to efficiently compute a starting address within an internal packet memory (IPM) configured to hold a packet received at the node. The starting address is used by direct memory access logic to merge a trailer of the packet stored in the IPM with a modified packet header generated by the forwarding engine. However, the size of the IPM is preferably not a binary number that can be easily manipulated by the forwarding engine when computing the starting address of the packet within the IPM. Therefore, the technique automatically adjusts the starting address to map to a correct location if the address exceeds the size of the IPM, while obviating the need for the forwarding engine to consider a wrap-around condition when computing the starting address.

Mapping technique for computing addresses in a memory of an intermediate network node

A method for decrementing a reference count in a multicast environment is provided that includes receiving an access request for a particle stored in a memory element. The memory unit is then accessed in response to the access request, the particle being read from the memory element. The particle includes a plurality of data segments, a selected one or more of which includes a first reference count associated with the particle. The particle is then presented to a target that generated the access request. The first reference count associated with the selected one or more data segments is then decremented in order to generate a second reference count. At least one of the plurality of data segments with the second reference count is then written to the memory element.

System and method for decrementing a reference count in a multicast environment

A method and apparatus manages packet header buffers of a forwarding engine contained within an intermediate node, such as an aggregation router, of a computer network. Processors of the forwarding engine add and remove headers from packets using a packet header buffer, i.e., context memory, associated with each processor. Addition and removal of the headers occurs while preserving a portion of the 'on-chip' context memory for passing state information to and between processors of a pipeline, and also for passing move commands to direct memory access (DMA) logic external to the forwarding engine. A wrap control function capability within the move command works in conjunction with the ability of the DMA logic to detect the end of the context and wrap to a specified offset within the context. That is, rather than wrapping to the beginning of a context, the wrap control capability specifies a predetermined offset within the context at which the wrap point occurs.

Method and apparatus for controlling packet header buffer wrap around in a forwarding engine of an intermediate network node

An apparatus and technique off-loads responsibility for maintaining order among requests directed to a same address on a split transaction bus from a processor to a split transaction bus controller, thereby increasing the performance of the processor. The present invention comprises an ordering circuit that enables the controller to defer issuing a subsequent (write) request directed to an address on the bus until a previous (read) request directed to the same address completes. By off-loading responsibility for maintaining order among requests from the processor to the controller, the invention enhances performance of the processor since the processor may proceed with program execution without having to stall to ensure such ordering. The ordering circuit maintains ordering in an efficient manner that is transparent to the processor.

Apparatus and technique for maintaining order among requests directed to a same address on an external bus of an intermediate network node

A sequence control mechanism enables out-of-order processing of contexts by processors of a symmetric multiprocessor system having a plurality of processors arrayed as a processing engine. The processors of the engine are preferably arrayed as a plurality of rows or clusters embedded between input and output buffers, wherein each cluster of processors is configured to process contexts in a first in, first out (FIFO) synchronization order. However, the sequence control mechanism allows out-of-order context processing among the clusters of processors, while selectively enforcing FIFO synchronization ordering among those clusters on an as needed basis, i.e., for certain contexts. As a result, the control mechanism reduces undesired processing delays among those processors.

Sequence control mechanism for enabling out of order context processing

An apparatus and technique off-loads responsibility for maintaining order among requests issued over a split transaction bus from a processor to a split transaction bus controller, thereby increasing the performance of the processor. A logic circuit enables the controller to defer issuing a subsequent (write) request directed to an address on the bus until all pending (read) requests complete. By off-loading responsibility for maintaining order among requests from the processor to the controller, the invention enhances performance of the processor since the processor may proceed with program execution without having to stall to ensure such ordering. The logic circuit maintains the order of the requests in an efficient manner that is transparent to the processor.

Growing community of inventors

Raleigh, NC, United States of America

Kenneth H Potter