Standard Microsystems Corporation

Other

Kenneth George Smalley

Ian F Harris

Steven Burstein

A method and apparatus for providing relocatable code storage in a multifunction controller or other integrated circuit which includes an embedded microprocessor and an internal memory. The relocatable code is initially stored in an external memory which is shared by the embedded microprocessor and other system processing elements such as a host CPU. During a system initialization, power-on reset or other predetermined event, a memory multiplexing circuit connects the address inputs of the internal memory to a read/write address bus, and connects the output of a jump data storage circuit to a code data output bus. The jump data storage circuit uses code addresses received from the embedded microprocessor to generate a jump instruction code which is supplied to the embedded microprocessor via the code data output bus. The embedded microprocessor is thereby forced to jump to a designated location in external memory which may include a transfer instruction directing the embedded microprocessor to transfer relocatable code from the external memory to the internal memory. The memory multiplexing circuit then configures the internal memory into an execution mode, in which the address inputs of the internal memory are connected to a code address bus and the data outputs of the internal memory are connected to the code data output bus. This ensures that the embedded microprocessor will have access to valid internal code after a system initialization or other predetermined event.

Relocatable code storage in an integrated circuit with an embedded microprocessor

A method and apparatus for controlling the access of multiple processors to a shared memory device in a computer or other processor-based system. An exemplary embodiment includes an embedded processor and a host processor, both of which share access to a single-port random access memory (RAM). An access control circuit is provided which includes a control register with a first storage element corresponding to the embedded processor and a second storage element corresponding to the host processor. The access control circuit utilizes access request bits stored in the first and second storage elements to generate a select signal which is applied to the select signal inputs of a group of multiplexers. The multiplexers select either the embedded processor or host processor control, address and data signal lines for connection to the single-port RAM. The access control circuit is configured such that the first processor to successfully set the access request bit in its corresponding storage element is granted temporary exclusive access to the RAM. The storage elements are interconnected such that the output of a given element drives a reset input of the other element. Once a given processor sets its access request bit and is thereby granted access to the shared RAM, the storage element interconnection prevents the other processor from setting its access request bit until the given processor relinquishes control of the RAM.

Method and apparatus for the sharing of a memory device by multiple

A method and apparatus for providing power management functions in a multifunction controller having an embedded microprocessor. An enter sleep mode indication is received in the microprocessor in the form of, for example, a command generated by a host central processing unit or an interrupt indicating a lack of system activity for a predetermined period of time. The clock input to the microprocessor is switched from a first clock source to a second clock source in response to the enter sleep mode indication. The main system supply may then be powered down by the microprocessor. The first clock source is then turned off after expiration of a first predetermined delay. The second clock is subsequently turned off after a second predetermined delay, to thereby place the system and the microprocessor into a sleep mode. While the system and microprocessor are in the sleep mode, an interrupt-handling portion of the microprocessor and a power control logic circuit remain powered off a low-current standby supply. Upon detection of a wake-up event, the second clock source is automatically started and applied to the microprocessor after a predetermined delay. The microprocessor can then process the wake-up event indicator, and if necessary power up the system and re-connect itself to the first clock source.

Method and apparatus for powder management in a multifunction controller

A method is disclosed for giving a host CPU direct access to the address space of an embedded microprocessor in a multifunction controller. The data path of the multifunction controller chip is modified to enable this direct access.

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Hauppauge, NY, United States of America

Kenneth George Smalley