Lsi Logic Corporation

Analog Devices,inc.

Lsi Corporation

Agere Systems Inc.

Analog Devices International Unlimited Company

Kenneth G Richardson

Donald Thomas McGrath

Scott C Savage

Robert D Waldron

Steven J Tanghe

Michael Straub

Brian Kirk Jadus

Ruida Yun

Kevin R Wrenner

Todd A Randazzo

Jonathan Alois Schmitt

Peter John Windler

Jonathan Kraft

Scott Allen Peterson

Matthew Russell

Kenneth Stanley Szajda

Eric A Sagen

Michael Collins

Deepak Gunasekaran

Ryan Schnell

Timothy McGonagle

Art Zirger

Tri Nguyen

Aspects of the present disclosure include a scalable proportional to absolute temperature (PTAT) hybrid circuit, comprising a bias mirror circuit configured to provide a zero temperature coefficient (ZTC) current, a PTAT control circuit configured to generate, based on the ZTC current, a PTAT current with a slope having a non-zero value, alter the PTAT current by at least scaling the PTAT current or changing the slope of the PTAT current to generate an altered PTAT current, and provide the altered PTAT current, a hybrid circuit configured to receive the ZTC current and the altered PTAT current, and output a larger current of the ZTC current and the altered PTAT current as a hybrid current.

Bias current with hybrid temperature profile

Aspects of the present disclosure include a hybrid circuit, including a first current sink configured to sink a zero temperature coefficient (ZTC) current, a second current sink configured to sink a positive temperature coefficient (PTC) current, a first transistor configured to provide a first current, a second transistor configured to provide a second current, a third transistor configured to provide a third current mirroring the ZTC current, a fourth transistor configured to provide a sum current of the first current and the third current, and a current mirror configured provide a hybrid current mirroring the sum current.

An apparatus and methods to operate the same to provide fast fault-detection on power semiconductor devices such as power transistors are disclosed. In some embodiment, a desaturation based fault-detection circuit for a power transistor is provided. The fault-detection circuit has an adaptable blanking time and a disconnect switch in the blanking mechanism that allow for quick enabling of fault-detection mechanisms to achieve fast fault detection times on power semiconductor devices.

Apparatus and method to achieve fast-fault detection on power semiconductor devices

A circuit to control a switching characteristic of a switching device. The circuit includes a driver circuit comprising an output port, where the driver circuit is configured to generate, at the output port, a control signal to actuate the switching device within a first time period. The control signal comprising at least one electrical pulse, where a pulse width of the at least one electrical pulse being shorter than the first time period. The circuit also includes a coupling circuit that is configured to use the control signal to actuate the switching device to establish a target switching characteristic of the switching device according to a modulation of the at least one electrical pulse. The control circuit is also configured to provide a greater impedance to the control signal than an impedance of the output terminal of the driver circuit.

Gate driver with pulsed gate slew control

For near field communications, inductive coils coupled to each communicating circuit are brought close together so that there is inductive coupling between the two coils. Data signals can then be relayed between the two circuits without any direct connection between them. However, the system is susceptible to common mode noise, such as ambient EMI. In addition to the 'active' coil pairs used for transmitting and receiving data, a pair of 'passive' coils is provided, proximate to the active coil pairs, that is only used for detecting the ambient EMI. The EMI signals detected by the passive coils are processed by a noise detector/processor, and the noise detector processor then controls the transmitters and/or receivers to at least partially compensate for the detected EMI signals. Transmit power or receiver thresholds may be controlled by the noise detector/processor to improve the signal-to-noise ratio, or other compensation techniques can be used.

EMI rejection for near field links

Micro-fabricated coils are described. In some situations, the micro-fabricated coils include interleaved coils. In some situations, pairs of interleaved coils are stacked with respect to each other, separated by an insulating material. In some situations, the interleaved coils have an S-shape. The interleaved coils may be employed in a galvanic isolator.

Coupled coils with lower far field radiation and higher noise immunity

An embodiment of a power supply circuit to generate a supply voltage for a gate driver circuit can include an isolated power supply circuit to receive a first voltage in a first isolated system and provide power to a cyclic charging power supply circuit, the cyclic charging power supply circuit providing a supply voltage to the gate driver circuit in a second isolated system, the isolated power supply circuit providing the power to the cyclic charging power supply circuit while the gate driver circuit drives a transistor in an on state. The isolated power supply circuit can include a control circuit to regulate the power provided to maintain or increase the supply voltage while the gate driver circuit drives the transistor in an on state. The power supply circuit can also include the cyclic charging power supply circuit to receive a second voltage in the second isolated system and provide the supply voltage to the gate driver circuit. The cyclic charging power supply circuit can include one or more of a bootstrap power supply circuit or a charge pump power supply circuit.

Power supply circuits for gate drivers

A drive system for multiple LED strings powered by a common line voltage. Current control circuits are connected in series with respective LED strings; each current control circuit includes a drive transistor (typically a FET) which causes a desired LED string current to be conducted. In one embodiment, the current conducted by a selected one of the LED strings is controlled by the line voltage regulation loop, while the currents conducted by the remaining LED strings are controlled by respective local current loops, thus avoiding conflicts between the local current and line voltage regulation loops. The LED string to be current regulated by the line voltage regulation loop can be determined by a variety of criteria, such as the current control circuit having the maximum FET gate voltage, the minimum FET source voltage, the minimum FET drain voltage, the maximum FET gate-source voltage, or the minimum FET drain-source voltage.

Multi-string LED drive system

A switching power supply controller which includes at least one switching element, and controls a switching cycle during which the switching elements are switched on and off to regulate the power supply's output voltage. The controller has a feedback signal which represents the output voltage, and a circuit node which conducts a current that is higher during a second portion of the switching cycle than it is during a first portion, such that the feedback signal varies with the current conducted by the node. To overcome feedback signal inaccuracies, a sampling circuit samples a signal which varies with the feedback signal only during the first portion of the switching cycle; the controller then regulates the output voltage in response to the sampled signal. The sampling circuit may be further arranged to produce an output which approximates the portion of the feedback signal waveform which is not sampled.

Switching power supply controller with selective feedback sampling and waveform approximation

The present inventions are related to systems and methods for pre-equalizer noise suppression in a data processing system. As an example, a data processing system is discussed that includes: a sample averaging circuit, a selector circuit, an equalizer circuit, and a mark detector circuit. The sample averaging circuit is operable to average corresponding data samples from at least a first read of a codeword and a second read of the codeword to yield an averaged output based at least in part on a framing signal. The selector circuit is operable to select one of the averaged output and the first read of the codeword as a selected output. The equalizer circuit is operable to equalize the selected output to yield an equalized output, and the mark detector circuit is operable to identify a location mark in the equalized output to yield the framing signal.

Circuits and methods for improved FET matching

Various embodiments of the present invention provide circuits and methods for improved FET matching. As one example, such methods may include providing two or more transistors. Each of the transistors includes a channel that varies in cross-sectional width from the source to the drain, and the transistors are matched one to another.

A method for producing a chip is disclosed. A first step of the method may involve fabricating the chip only up to and including a first metal layer during a first manufacturing phase such that an input/output (I/O) region of the chip has a plurality of slots, where each of the slots has a plurality of first transistors. A second step of the method may involve designing a plurality of upper metal layers above the first metal layer in response to a custom design created after the first fabricating has started, the upper metal layers interconnecting a plurality of the first transistors to form a plurality of mixed-signal building block functions. A third step of the method may involve fabricating the chip to add the upper metal layers during a second manufacturing phase.

Use of configurable mixed-signal building block functions to accomplish custom functions

An apparatus comprising an integrated circuit having (i) a number of regions each pre-diffused and configured to be metal-programmed and (ii) a plurality of pins configured to connect the integrated circuit to a socket. A logic portion may be implemented on the integrated circuit (i) configured to implement integrated circuit operations and (ii) having one or more I/O connections and one or more supply connections. A first group of the pre-diffused regions are metal-programmed and coupled to said I/O connections. A second group of the pre-diffused regions are metal-programmed and coupled to the supply connections.

Distributed relocatable voltage regulator

An apparatus including a base layer of a platform application specific integrated circuit (ASIC), a mixed-signal function and a built-in self test (BIST) function. The base layer of the platform ASIC generally includes a plurality of pre-diffused regions disposed around a periphery of the platform ASIC. Each of the pre-diffused regions is generally configured to be metal-programmable. The mixed-signal function may include two or more sub-functions formed with a metal mask set placed over a first number of the plurality of pre-diffused regions. The BIST function may be formed with a metal mask set placed over a second number of the plurality of pre-diffused regions. The BIST function may be configured to test the mixed-signal function and present a digital signal indicating an operating condition of the mixed-signal function.

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Longmont, CO, United States of America

Kenneth G Richardson