Texas Instruments Corporation

Kenneth G Buss

Ross Eliot Teggatz

Andrew Marshall

Taylor R Efland

Stephen C Kwan

Joseph A Devore

Chin-Yu Tsai

Thomas A Schmidt

David R Cotton

Norman L Culp

Joe A Devore

Eric E Campos

An integrated SCR-LDMOS device (10) having a p+ region (13) in the drain region (12), but otherwise similar to a conventional LDMOS transistor. The device (10) may be implemented as a modification of a non-planar LDMOS (FIGS. 1 and 2). An alternate embodiment, device (30), may be implemented as a modification of a planar LDMOS (FIG. 3). In either case, the added p+ region (13, 37) provides the device (10, 30) with two parasitic bipolar transistors in an SCR configuration (FIGS. 4A and 4B).

Integrated SCR-LDMOS power device

An optimized power output clamping structure, includes a power output transistor having a first breakdown voltage and a breakdown structure having a second breakdown voltage coupled to the power output transistor. The second breakdown voltage is less than the first breakdown voltage and follows the first breakdown voltage across all temperature and semiconductor process variations. This feature allows a reduction in breakdown voltage guardbanding and increases output structure reliability. A method of protecting a circuit from inductive flyback is also disclosed. The method includes the steps of driving an inductive load with drive circuitry, turning off the inductive load, and clamping an inductive voltage at a voltage magnitude that protects the drive circuitry from breakdown across all temperature and processing variations.

Optimized power output clamping structure

A method and apparatus for programmable current limits is provided in which a plurality of current limit programmable cells (44 and 46) are programmed with a current limit. Output circuitry (14 and 16) which outputs current is limited by current limit circuitry (20, 24, 38, 40, and 42) when the output current reaches the programmed current limit.

Method and apparatus for programmable current limits

Circuitry (46, or 28 and 70) for thermally separating a power integrated circuit device (12) from a plurality of other such devices (14, 16, and 18) on a common power integrated circuit chip (10) operate when the device (12) reaches a thermal shutdown temperature setpoint (56) with an output current at a predetermined current limit (54). The circuitry 46, or 28 and 70 switches the output current to a shutdown current level (57) until the device (12) reaches a predetermined lower temperature setpoint (58). Circuitry (46, or 28 and 70) restores the output current level to the predetermined current limit only after the device (12) reaches both the predetermined lower temperature setpoint (58) and a predetermined circuit setpoint (62 or 74). The circuit setpoint (62 or 74) associates with the temperature of the device (12) and may be either a yet lower temperature setpoint (62) or a specified time delay (74). The above steps are repeated to lower the average temperature of the device (12) and thereby thermally separate the device (12) from the other of such devices (14, 16 and 18) on the common power integrated circuit chip (10).

Method and apparatus for thermally separating devices on a power

A circuit capable of driving inductive loads below a chip substrate voltage level while minimizing on-chip power dissipation and eliminating parasitic effects. Two negative voltage drive modes are included in the circuit design. The first drive circuit forces a low negative voltage referenced to the circuit output voltage across an inductive load referenced to ground to provide a slow recirculation of the current in the inductive load. The second drive circuit forces a large negative voltage referenced to the circuit output voltage across the inductive load to provide a fast collapse of the inductive load. The switching regulator switches off when the current to the inductive load reaches a first value and switches on when the recirculating current from back e.m.f. reaches a second value. The switching regulator initially provides a higher level of power when first tuned on.

Negative voltage clamp circuit for controlling currents in inductive

An annunciator is disclosed which has an improved charging circuit for storing the energy of a ring signal received via an improved Schottky diode bridge rectifier, and an oscillator-driven variable divider which actuates an audible output device when the stored charge exceeds a threshold level.

Annunciator

A television tuning system having a non-volatile memory for storing digital tune words is electrically updated by a microcomputer type architecture control circuitry. A ROM memory matrix is provided for the storage of VHF minimum and maximum binary tune words corresponding to each of twelve VHF channels in addition to a UHF minimum and maximum binary tune word encompassing all possible 72 UHF channels. Tuning of individual VHF and UHF chanels is accomplished by incrementing or decrementing a given tune word within the minimum and maximum limits established in the ROM memory matrix by means of a microcomputer processing approach.

Microcomputer processing approach for a non-volatile TV station memory

A television tuning system having a non-volatile memory for storing digital tune words is electrically updated by a microcomputer type architecture control circuitry. A ROM memory matrix is provided for the storage of VHF minimum and maximum binary tune words corresponding to each of twelve VHF channels in addition to a UHF minimum and maximum binary tune word encompassing all possible 72 UHF channels. Tuning of individual VHf and UHF channels is accomplished by incrementing or decrementing a given tune word within the minimum and maximum limits established in the ROM memory matrix by means of a microcomputer processing approach.

Growing community of inventors

Dallas, TX, United States of America

Kenneth G Buss