Intel Corporation

Kenneth Foust

Amit Kumar Srivastava

Duane G Quiet

George Vergis

Rajesh Bhaskar

Renzhi Liu

Nobuyuki Suzuki

Tolga Acikalin

Zhen Zhou

Chia-Pin Chiu

Kai Xiao

Mikal Hunsaker

Zuoguo Wu

Karthi R Vadivelu

Bruce L Fleming

Ajaya V Durg

Zhenyu Zhu

Tae Young Yang

Myron Loewen

Janusz Jurski

Richard Dorrance

Enrico David Carrieri

Jong-Ru Guo

Eduardo Alban

Jason A Mix

Rajasekaran Andiappan

Matthew A Schnoor

Kevin J Daniel

Daqiao Du

Cheng-Yuan Chin

Tae-Young Yang

Rodolfo E Camacho-Aguilera

Johanny Escobar Pelaez

Sundar Iyer

Rahul Bhatt

Xianfeng Ding

The present disclosure relates to a device which includes a processor configured to: select, using sensor data, an error correction code from two or more error correction codes, the sensor data representing a physical state of the processor and/or the device; generate channel-coded data by channel-coding input data using the selected error correction code; and provide a representation of the channel-coded data to a transmitter for wireless data transmission.

Wireless device and methods for dynamic channel coding

A package substrate may include a circuit and a leaky surface wave launcher. The circuit may perform engineering tests and end-user operations using sideband signals. The leaky surface wave launcher may perform near field wireless communication. The leaky surface wave launcher may include a via and a strip line. The via may be electrically coupled to the circuit. The via may provide the sideband signals to and receive the sideband signals from the circuit. The strip line may be electrically coupled to the via. The strip line may be excited by the sideband signals to wirelessly couple the leaky surface wave launcher with an external device. The strip line and the via may be unbalanced such that the strip line generates a leaky wave that propagates at least a portion of the package substrate and an environment proximate the package substrate.

Near field wireless communication system for mother to package and package to package sideband digital communication

In various aspects, a package system includes at least a first package and a second package arranged on a same side of the package carrier. Each of the first package and the second package comprises an antenna to transmit and/or receive radio frequency signals. A cover may be arranged at a distance over the first package and the second package at the same side of the package carrier as the first package and the second package. The cover comprises at least one conductive element forming a predefined pattern on a side of the cover facing the first package and the second package. The predefined pattern is configured as a frequency selective surface. The package system further includes a radio frequency signal interface wirelessly connecting the antennas of the first package and the second package. The radio frequency signal interface comprises the at least one conductive element.

Package system and package

In one embodiment, a host controller includes: a first input/output (I/O) buffer to couple to a first communication line of an interconnect; a second I/O buffer to couple to a second communication line of the interconnect; and a device group selection circuit to dynamically cause the first communication line to communicate a clock signal to a first device group including one or more first devices to couple to the interconnect and dynamically cause the second communication line to communicate a data signal to the first device group when a communication is to be addressed to at least one of the one or more first devices of the first device group, such that the communication is transparent to at least another device group to couple to the interconnect. Other embodiments are described and claimed.

Method, apparatus and system for device transparent grouping of devices on a bus

In an embodiment, a host controller includes a clock control circuit to cause the host controller to communicate a clock signal on a clock line of an interconnect, the clock control circuit to receive an indication that a first device is to send information to the host controller and to dynamically release control of the clock line of the interconnect to enable the first device to drive a second clock signal onto the clock line of the interconnect for communication with the information. Other embodiments are described and claimed.

Method, apparatus and system for dynamic control of clock signaling on a bus

In one embodiment, an apparatus includes: a peer-to-peer (P2P) control circuit to issue a P2P communication request to a bus master of a multi-drop interconnect to request authorization to send a P2P transaction to at least one slave device coupled to the multi-drop interconnect; a transmitter to transmit the P2P transaction to the at least one slave device when the bus master grants the authorization for the P2P transaction; and another transmitter to output the clock signal to the multi-drop interconnect during the P2P transaction. Other embodiments are described and claimed.

System, apparatus and method for peer-to-peer communication on a multi-drop interconnect

In an embodiment, a host device includes: a transceiver to communicate information on an interconnect; a controller to control operation of the transceiver and to be a master for the interconnect; and a role transfer logic to cause a secondary device to be the master for the interconnect when at least a portion of the host device is to enter into a low power. Other embodiments are described and claimed.

Method, apparatus and system for role transfer functionality for a bus master

In one embodiment, an apparatus includes: a processing circuit to execute instructions; and a host controller coupled to the processing circuit to perform a key exchange with a second device to couple to the apparatus via a bus to which a plurality of devices may be coupled, and in response to a successful completion of the key exchange, enable secure communication with the second device. Other embodiments are described and claimed.

System, apparatus and method for secure communication on a bus

In one embodiment, an apparatus includes an input/output (I/O) circuit to communicate information at a selected voltage via an interconnect to which a plurality of devices may be coupled, and a host controller to couple to the interconnect. The host controller may include a supply voltage policy control circuit to initiate a supply voltage policy exchange with a first device to obtain a first supply voltage capability of the first device and to cause the I/O circuit and the first device to be configured to communicate via the interconnect at a first supply voltage based on the first supply voltage capability. Other embodiments are described and claimed.

Method, apparatus and system for power supply policy exchange on a bus

Embodiments of the present disclosure may relate to a host controller that includes processing circuitry to identify an inter-integrated circuit (IC) out-of-band interrupt (OBI) received on a general purpose input-output (GPIO) pin from an IC device that is unable to generate an improved inter-integrated circuit (I3C) bus an I3C in-band interrupt (IBI). The processing circuitry may further generate, based on the IC OBI, an I3C IBI that includes information related to the IC OBI. The host controller may further include transmission circuitry to transmit the I3C IBI on an I3C bus. Other embodiments may be described and/or claimed.

Out-of-band interrupt mapping in MIPI improved inter-integrated circuit communication

In an embodiment, a host controller is to couple to an interconnect to which a plurality of devices may be coupled. The host controller may include: a first driver to drive first information onto the interconnect according to a bus clock signal; a first receiver to receive second information from at least one of the plurality of devices via the interconnect according to the bus clock signal; and a clock generation circuit to generate the bus clock signal having an asymmetric duty cycle. Other embodiments are described and claimed.

System, apparatus and method for controlling duty cycle of a clock signal for a multi-drop interconnect

In one embodiment, a flash sharing controller is to enable a plurality of components of a platform to share a flash memory. The flash sharing controller may include: a flash sharing class layer including a configuration controller to configure the plurality of components to be flash master devices and configure a flash sharing slave device for the flash memory; and a physical layer coupled to the flash sharing class layer to communicate with the plurality of components via a bus. Other embodiments are described and claimed.

System, apparatus and method for sharing a flash device among multiple masters of a computing platform

An apparatus is described. The apparatus includes a DIMM hub circuit. The DIMM hub circuit includes first bus interface circuitry, control circuitry and second bus interface circuitry. The first bus interface circuitry is to receive header information and payload information from a host. The control circuitry is to process the header information and recognize that the payload is to be passed to a target component that is coupled to the DIMM hub circuit through a second bus that is a same type of bus as the first bus. The second bus interface circuitry to send the payload information over the second bus to the target component, wherein, the payload information is to include embedded header information to be processed by the target component.

Growing community of inventors

Beaverton, OR, United States of America

Kenneth Foust