Cadence Design Systems, Inc.

International Business Machines Corporation

Kenneth Ferguson

Gilles S C Lamant

David J Mallon

Arnold Ginetti

Gilles Lamant

Kenneth Mackie

Scott Whitney Gould

Terrance John Zittritsch

Brian A Worth

Allan Robert Bertolet

Eric Ernest Millham

Randy Bishop

Yuan-Kai Pei

Ronald Raymond Palmer

Jean-Marc Bourguet

Sravasti Gupta Nair

Min-Ching Lin

Christopher Stewart

Monika Bijoy

Thomas Wilson

In the context of electronic design automation and particularly circuit layout design software tools, systems and methods for incremental chaining of circuit devices (or, more generally, 'figures,' which can include instances and pins) permit user-interactive abutment and placement. Selection of one or more anchor figures highlights chaining candidates which can be automatically chained to the anchor figure(s) upon selection, as with a single mouse click. As compared to manual interactive abutment or automatic batch-mode chaining, incremental chaining offers improved usability, reduced manual effort, and the opportunity for user interaction as a chain is constructed, because the user is permitted interventions at any point in the chaining process for altering device parameters or characteristics.

Incremental chaining in the presence of anchored figures

Disclosed herein are embodiments of systems, methods, and products using a center access direction for pin figures during an abutment of instances in an integrated circuit (IC) design. Using a center access direction allows an electronic design automation (EDA) tool to overlap the centers of the pin figures to be merged. Once the centers of the pin figures are overlapped, the EDA tool runs one or more merging and optimization algorithms to abut the circuit devices containing the pin figures. The EDA tool therefore is computationally efficient and yet provides more functionality: unlike the conventional system, the EDA tool does not have to align the pin figures and calculate an offset to overlap the pin figures post alignment. Furthermore, the EDA tool can overlap the pin figures from any angle and is not confined to rectilinear access direction of the conventional systems.

Methods and systems for centering of pins during instance abutment

Disclosed herein are systems and methods that allow a layout editor function, presented in a graphical user interface, of an EDA, to indicate certain layout instances or 'cell views' as 'transparent.' The instances are indicated as transparent using various layout editor commands or layout designer markers. Unlike conventional solutions, a binder within the layout editor of the EDA is not required to bind layout transparent instances to corresponding instances in a related schematic design file or records. Instead, the EDA may identify non-transparent instances at a lower-level of the layout design's hierarchy to bind, because the systems and methods described herein provide for a transparent instance container at a hierarchically higher-level.

Systems and methods for binding mismatched schematic and layout design hierarchy

Methods and systems of an electronic circuit design system described herein provide a new abutment tool in which a chain post-processing function is called once per resultant chain of abutted instances after each chain is fully formed in a layout. In an embodiment, a process design kit (PDK) abutment update function is enhanced to support a new chain processing event that facilitates a creation of new top level figures in a cell view in which the chain lives, and further facilitate adjustment of parameters of instances of programmable cells in the chain.

Methods and systems for customizable editing of completed chain of abutted instances

The subject system and method are generally directed to the user-friendly insertion of at least one device, and optionally chains of devices, into at least one pre-existing chain of interconnected devices within a graphical representation of a circuit design such as a circuit layout, circuit mask, or a schematic. The system and method provide for discerning the intended insertion points and performing remedial transformations of the devices within the chains to ensure compliance with both structural and operational requirements of the circuit design.

System and method for automatically reconfiguring chain of abutted devices in electronic circuit design

Systems and methods to enable a user to edit subMaster content of selected instances of an electronic layout design, including editing the contents of selected instances of an existing subMaster of an EDA design, generating a new subMaster to incorporate the modified contents of the selected instances, and binding the new subMaster to the selected instances without losing the design hierarchy of the layout design.

Systems and methods of editing cells of an electronic circuit design

In one embodiment a new method to address configuring a logical design and libraries of design elements with additional information is proposed that may be used to create a physical design from that logical design. Logical designs may be generic, while physical design libraries are normally targeted towards specific technology. Consequently, there can be a mapping from the cells in a logical library to cells which correspond to their implementation in a physical library. In one embodiment, annotations required to map from logical design to physical design may be stored in a separate design view. In one embodiment the user can modify the physical mapping attributes of cells, instances, and occurrences in the logical design and save the modifications back to the physical configuration view.

Methods and systems for physical hierarchy configuration engine and graphical editor

A programmable array having programmable logic cells, a programmable interconnect network and a programmable I/O system. Two I/O interfaces are provided for respective logic cells about the perimeter of the array. The I/O interfaces comprise input, output and enable paths. Each of these paths has an associated multiplexer. An I/O routing network is positioned about the perimeter of the array. Conductors connecting the I/O interface multiplexers to the programmable interconnect network also intersect, and can be programmably connected to, buses of the I/O routing network.

Growing community of inventors

Edinburgh, United Kingdom

Kenneth Ferguson