Intel Corporation

Kenneth E Wojciechowski

Kerry Dean Tedrow

Mase J Taub

Albert Fazio

Gregory E Atwood

Johnny Javanifard

Stephen N Keeney

Joseph W Tsang

A charge pump having an output diode with a zero voltage drop. The present charge pump may be a multiple stage charge pump that may operate more efficiently than prior charge pumps by substantially removing the voltage drop across the output diode. The last stage in the charge pump receives a second input clock signal. The output diode includes a switch device coupled to a bootstrapping circuit which receives a third input clock signal and a fourth input clock signal. The third input clock signal and the fourth input clock signal are either non-overlapping high clock signals or non-overlapping low clock signals. A specified relationship between the second clock signal and the third clock signal, and a specified relationship between the third clock signal and the fourth clock signal are required to allow the bootstrapping circuit to properly augment the voltage passed through the switch device in the output diode.

Method and apparatus for removal of VT drop in the output diode of

A zero voltage drop switch in a negative switch circuit. The zero voltage drop switch substantially passes the entire negative voltage signal provided by a negative voltage source to the output of the negative switch circuit. The zero voltage drop switch includes a switch circuit coupled to a bootstrapping circuit which augments the voltage passed by the switch circuit. The bootstrapping circuit includes a pair of capacitive devices that receive a pair of non-overlapping clock signals.

Zero voltage drop negative switch for dual well processes

A voltage detector circuit. The voltage detector circuit determines when a supply voltage exceeds a predetermined threshold voltage. According to one embodiment, the voltage detector circuit is used in a nonvolatile memory device to determine whether a programming supply voltage is five volts or twelve volts.

Low current reduced area programming voltage detector for flash memory

A voltage detector including first and second current paths between a source voltage at a first level and current-limiting device joined to a second level of voltage, each path including an essentially-identical flash EEPROM memory device, one of the memory devices being programmed to have a lower threshold voltage than the other memory device; a circuit for providing a voltage to be measured to gate terminals of one of the memory devices and a percent of the voltage to be measured to the of one of the memory devices having the lower threshold voltage, and an output device connected to measure the current flowing through one of the current paths, the output device being arranged to conduct when current through the first path is greater than current through the second path and not to conduct when current through the first path is less than current through the second path.

High precision voltage detector utilizing flash EEPROM memory cells

A voltage regulation circuit that includes a sample and hold circuit for sampling an input voltage and for holding a reference voltage generated in response to the input voltage. The sample and hold circuit includes a capacitor that holds the reference voltage. The voltage regulation circuit also includes a regulator circuit coupled to the capacitor of the sample and hold circuit. The regulator circuit outputs an output voltage using the reference voltage supplied by the capacitor. The voltage regulation circuit may be used to provide a high precision programming voltage for programming memory cells having two or more analog states.

High precision voltage regulation circuit for programming multiple bit

A voltage detector circuit for detecting when an input voltage exceeds a trip-point voltage. The voltage detector circuit includes a nonvolatile memory cell having a select gate coupled to the input voltage, a drain coupled to a first node, a source coupled to system ground, and a floating gate. The nonvolatile memory cell is used primarily as a pull-down transistor, and the threshold voltage of nonvolatile memory is programmed to be the trip-point voltage such that the first node is set to system ground if the input voltage exceeds the trip-point voltage. The voltage detector circuit also includes a first transistor having a control electrode coupled to a biasing voltage, a first terminal coupled to the first node, and a second terminal coupled to a supply voltage. The control electrode is operative to couple the first terminal to the second terminal in response to the biasing voltage. The first transistor sets the first node to the input voltage if the input voltage is less than the trip-point voltage. The voltage detector further includes an output circuit coupled to the first node. The output circuit is operative to indicate whether the input voltage exceeds the trip-point voltage in response to the voltage of the first node.

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Folsom, CA, United States of America

Kenneth E Wojciechowski