Panasonic Technologies, Inc.

Kenneth E Vavreck

Kevin J Stec

Jerome D Shields

Lee R Dischert

Clarence J-y Hau

A system for converting a digital input signal having a vertical and horizontal dimension into a digital output signal having a different horizontal and vertical dimension than that of the digital input signal. The digital input signal is fed into a first memory which stores the input signal. A horizontal resampling filter is used for converting the horizontal dimension of the digital input signal to the horizontal dimension of the desired output signal. The output from the horizontal resampling filter is transposed so that the vertical dimension of the output signal is oriented in a horizontal orientation. The transposed signal is then stored in a second memory. The transposed signal with the resampled horizontal dimension from the second memory is fed into a vertical resampling filter which converts the vertical dimension information of the transposed signal to the desired format of the output signal. This vertically resampled signal is then transposed so that the horizontal and vertical dimensions are oriented like that of the digital input signal. The re-tranposed signal is then stored in a third memory as the digital output signal.

Flexible parallel processing architecture for video resizing

A clocking circuit and method for phasing a signal with an unknown phase to a clock signal includes a time requirement duration (TRD) signal which has two states and the duration of one of the states is indicative of a combined setup and hold time requirement for the storage device intended to capture the unknown phase signal. The TRD signal is then clocked as a function of the unknown phase signal and called a toggle clock phase (TCP) signal. The TCP signal is then used to modify the phase of a clock enable for the storage device signal to ensure adequate setup and hold time for the clocking of the unknown phase signal.

Apparatus and method for reliably clocking a signal with arbitrary phase

A sample rate conversion system converts from an input sample rate stream having a predetermined input sample rate to an output sample stream having a predetermined output sample rate by interpolating output samples from the input samples using first and second approximate sample rate ratios. The system includes circuitry which selects a sequence of interpolation filters from among a set of filters, the sequences being defined by one of these approximate ratios, and circuitry which monitors the magnitude of the accumulated error introduced by the approximation. When this accumulated error becomes greater than a threshold, the system changes to use a further sequence of interpolation filters based on the other approximate ratio. The accumulated error changes in a positive sense with each successive sample while one of the two approximate ratios is used. The accumulated error changes in a negative sense with each successive sample while the other of the two approximate ratios is used. The system switches between these sample rate ratios to maintain the magnitude of the position error of the interpolated samples below a predetermined threshold value. A sample rate conversion system which converts a television signal in CCIR (601) format into a Phase Alternate Line (PAL) video signal is disclosed.

Approximating sample rate conversion system

A video signal processing system uses a sequence of interpolation filters to resample a 125M video signal to produce a 244M signal. In addition, the system allows an operator to specify a desired subcarrier-to-horizontal sync (SCH) phase and a desired horizontal position. The system automatically adjusts the starting point in the sequence of filters used for the resampling operation to implement each of the requested phase shifts.

Apparatus for adjusting the timing of sampled data signals in a

A system for converting a digital component video signal having timing information contained therein to a digital composite video signal is described. The system has a decoder for extracting the timing information from the digital component signal, a digital memory means for storing portions of the desired digital composite signal, a memory control means for extracting the portions of said desired signal from the digital memory means in response to the timing information and a multiplexing means for combining the portions of the signal extracted from the digital memory in response to timing information of the digital component signal.

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Maple Shade, NJ, United States of America

Kenneth E Vavreck