Raytheon Company

Kenneth E Prager

Lloyd J Lewins

Harry B Marr

William D Farwell

Julia L Karl

Michael D Vahey

Daniel G Thompson

Philip T Shimon

Micahel D Vahey

James T Whitney

A low-power digital logic architecture exhibits the same logic and voltage level behavior as standard digital logic. A logic switch and a pair of unidirectional switches are used to control the direction of charge flow in a switched-inductor capacitor (SLC) circuit, allowing the inductor to pull charge back-and-forth from one side of the load capacitor to the other to both switch the logical state at the top of the capacitor and to recycle and store the charge in the capacitor itself.

Low-power digital logic using a Boolean logic switched inductor-capacitor (SLC) circuit

An asynchronous pipeline structure includes a plurality of functional blocks comprising dynamic logic, each block precharged to an idle state responsive to a precharge control signal applied thereto, with each block, upon being precharged, receiving input data thereto for processing, and holding output data generated thereby during an evaluate phase, independent of a reset of the input data; for each block, a completion detector circuit coupled to the output of the functional block, the completion detector circuit generating an acknowledgement signal that indicates validity or absence of data at the output of the block; and for each block, a precharge control circuit generating a precharge signal, wherein for a given block, a first input to the precharge control circuit comprises the acknowledgment signal from a downstream completion detector, and second input to the precharge control circuit comprises the precharge signal from an upstream precharge control circuit.

Minimizing power consumption in asynchronous dataflow architectures

A data flow controller for reconfigurable computers. The novel data flow controller includes a first circuit for selecting one of a plurality of operating conditions and a second circuit for determining if the selected condition is met and outputting a control signal accordingly. In an illustrative embodiment, the operating conditions include: when all enabled data available signals are asserted and all enabled space available signals are asserted; when any enabled data available signal is asserted and all enabled space available signals are asserted; when all enabled data available signals are asserted and any enabled space available signal is asserted; and when any enabled data available signal is asserted and any enabled space available signal is asserted. By allowing a configurable element to operate under different possible conditions, data flow signals can also then be used to control what operation the element performs, in addition to controlling when.

Means of control for reconfigurable computers

A digital signal processing apparatus includes a digital circuit device having one or more elements configured to process digital data; a power supply configured to deliver a controllable operating voltage for the one or more elements; control logic configured to receive feedback signals from each of the one or more elements, the feedback signals indicative of a rate at which data is moving through each individual element; and the control logic configured to output a control signal to the power supply so as to cause the power supply to reduce the operating voltage for the one or more elements responsive to a decreasing workload detected therein, and to cause the power supply to increase the operating voltage for the one or more pipelines responsive to an increasing workload detected therein.

Methods for tracking the relative velocity between a vehicle and a target that uses both a measured velocity as well as an estimate of the velocity that is based on tracking the peaks in a laser vibrometer return signal.

Doppler tracking in presence of vehicle velocity uncertainty

A reconfigurable processor architecture. A reconfigurable processor is an array of a multiplicity of various functional elements, between which the interconnections may be programmably configured. The inventive processor is implemented on a single substrate as a network of clusters of elements. Each cluster includes a crossbar switching node to which a plurality of elements is connected via ports. Additional ports on the crossbar switching node connect to the switching nodes of nearest neighbor clusters. The crossbar switching nodes allow pathways to be programmably set between any of the ports, and any pathway may be set to be either registered or unregistered. The use of clusters of processing elements allows complete freedom of local connectivity for effective configuration of many different processing functions. Wide area interconnection is more restricted, but, since it is less used, does not significantly restrict configurability. The inventive processor thus provides 1) high configurability with a low cost of switching network overhead; 2) constant clock speed, independent of configuration; and 3) very high clock speed since all communication is local or nearest neighbor.

Reconfigurable processor with alternately interconnected arithmetic and memory nodes of crossbar switched cluster

A communication path includes N channels or information pathways, each of which is bidirectional, i.e. each channel may be set to either send or receive. The number of send channels (S) and receive channels (R) is programmably set, such that S&plus;R&equals;N. The total bandwidth is N*B, where B is the bandwidth of each channel, and the send and receive bandwidths can be adjusted to any values such that N*B&gE;(S*B&plus;R*B), on an as-needed basis depending on the processing algorithms being executed.

Growing community of inventors

Granite Bay, CA, United States of America

Kenneth E Prager