Hewlett-packard Company

Other

Kenneth E Posse

Kenneth Paul Parker

Kevin W Keirn

Anne Elizabeth Dudfield

Stig Oresjo

George L Booth

Patricia Monterio

Michael A Lassner

A system for efficient utilization of multiple test systems may include an apparatus for testing an electronic circuit board, which comprises a number of computer readable media containing computer readable program code comprising code for a test analysis system that interfaces with at least two test systems. The test analysis system reads a description of said board's board topology and analyzes a number of potential defects of said board based on that description. The test analysis system creates at least two test procedures for the at least two test systems by creating a first test procedure to test the electronic circuit board on a first test system of the at least two test systems. The system then creates at least one other test procedure to test the electronic circuit board on at least one other test system of the at least two test systems. The system then optimizes the at least one other test procedure based on at least one other of the at least two test procedures created for the at least two test systems to reduce redundancies in the at least two test procedures.

System for efficient utilization of multiple test systems

A digital signal detector for sampling the state of a high speed digital signal occurring at a test node in a digital circuit which exhibits the same behavior with repeated applications of the same inputs. The digital signal detector samples the state of a test circuit node at discrete intervals in time and stores the digital levels with timing reference information. The stored information is then compared to the expected behavior of the tested node for analysis of delay-type and other parametric faults, such as performance faults. The digital signal detector includes a state discriminator which determines the state of the input digital signal by comparing its voltage level to one or more threshold voltages. The digital signal detector also includes a memory unit which stores the signal state information upon receipt of a memory strobe signal generated by a memory delay control circuit which delays the application of the memory strobe signal by a predetermined amount of time after the receipt of a clock pulse. The stored digital signal states can be later retrieved from the memory unit for evaluation of the input digital signal.

Method and apparatus for the capturing and characterization of

A method for generating improved detection and diagnostic test patterns and for improving the diagnostic resolution of interconnect testing of a circuit is based on the premise that short-circuits are most likely to result from solder bridges between closely adjacent pins. In a first embodiment, an optimal boundary-scan test pattern is generated. In a second embodiment, boundary-scan test diagnosis is enhanced by utilizing x,y coordinate data corresponding to the physical location of devices on the tested circuit. In a third embodiment, diagnosis of unpowered short-circuit testing is enhanced.

Enhanced interconnect testing through utilization of board topology data

A method for testing a circuit board having both boundary-scan and non-boundary-scan devices is provided. The test method distinguishes boundary-scan nodes from non-boundary-scan nodes and uses cartesian coordinates (X,Y) of every pin of every device on the circuit board to determine a number of sets of non-boundary-scan nodes that are within a predetermined distance 'R' from a device pin coupled to a boundary-scan node. The number of sets of non-boundary-scan nodes are grouped into 'independent' groups which can be tested in parallel. A test cycle is performed by testing independent non-boundary-scan nodes in parallel by forcing drivers in the boundary-scan devices to a first logic state, and forcing each of the non-boundary-scan nodes to another logic state for a brief interval. Receivers on the boundary-scan devices capture a response vector during the brief interval, which is scanned out of the circuit board for evaluation. The response vector reflects which of the nodes has failed, and cartesian coordinate data giving the precise location of any faulty node(s) is returned to user.

Powered testing of mixed conventional/boundary-scan logic

The (X,Y) positions of the nodes in a circuit containing boundary scan components and non-boundary-scan components are stored in a computer. The computer selects a set of non-boundary scan nodes within a radius R of a selected boundary-scan node, R being the length of solder bridges in the circuit. A logic 0 voltage is applied to the set and a boundary-scan test is performed. If the boundary-scan test fails, a fault is declared in the circuit between the set and the selected boundary-scan node. A logic 1 voltage is applied to one of the nodes in the set, and the test repeated. If the test returns different results, the fault is declared between that one node and the selected boundary-scan node. A time limit is established for each non-boundary scan node corresponding to the length of time a short in that node can be tolerated. The boundary-scan nodes in the circuit are tested in the order of ascending time limits in its associated set. Power is cut off to the circuit if the time limit of a node not yet tested, or tested and failed, is exceeded.

An apparatus for diagnosing faults in a device equipped with boundary-scan test capability stores serial test data upon detection of a fault in a device under test (DUT). Test data corresponding to a frame vector associated with the fault is formatted so that all information from parallel tester inputs and TAP scan registers can be simultaneously analyzed. A method for diagnosing faults is also disclosed.

Boundary-scan test method and apparatus for diagnosing faults in a

The (X,Y) positions of the nodes in a circuit containing boundary scan components and non-boundary scan components are stored in a computer. The computer selects a set of non-boundary scan nodes within a radius R of a selected boundary-scan node, R being the length of solder bridges in the circuit. A logic 0 voltage is applied to the set and a boundary-scan test is performed. If the boundary-scan test fails, a fault is declared in the circuit between the set and the selected boundary-scan node. A logic 1 voltage is applied to one of the nodes in the set, and the test repeated. If the test returns different results, the fault is declared between that one node and the selected boundary-scan node. A time limit is established for each non-boundary scan node corresponding to the length of time a short in that node can be tolerated. The boundary-scan nodes in the circuit are tested in the order of ascending time limits in its associated set. Power is cut off to the circuit if the time limit of a node not yet tested, or tested and failed, is exceeded.

An on-chip pull-up which can be selectively enabled/disabled comprises a pull-up transistor (e.g., an FET) connected between the line to be pulled up/down and a bias voltage (e.g., a positive voltage V.sub.DD or a negative voltage V.sub.SS). The control lead (e.g., gate lead) of the transistor is then made externally accessible. Connecting the control lead to V.sub.DD or V.sub.SS either enables or disables the pull-up depending on the particular transistor.

On-chip pull-up circuit which may be selectively disabled

Disclosed is a method for compressing sequences of data-vectors, which sequences are to be used for testing circuit boards with the aid of a circuit board testing machine. The method involves an initial compression of the data-vector sequence followed by a so-called K-T transformation of the remaining data-vectors. The initial compression involves eliminating redundant data-vectors from the initial sequence and retaining only the unique data-vectors together with sequencing information indicating where in the initial sequence each unique-data vector occurred. The K-T transformation involves a bitwise logical exclusive-OR operation (XOR) whereby the remaining data-vector sequence is K-T transformed thereby further compressing the sequence without losing any of the original sequence information.

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Fort Collins, CO, United States of America

Kenneth E Posse