International Business Machines Corporation

Kenneth E Plambeck

Casper A Scalzi

Lisa Cranton Heller

Erwin F Pfeffer

Timothy John Slegel

Richard J Schmalz

Balakrishna Raghavendra Iyer

Steven Jay Greenspan

Richard I Baum

Carl Edward Clark

Bhaskar Sinha

Michael Gerard Mall

Alan G Ganek

Craig Alan Friske

Terry L Borden

James Lum

Justin R Butwell

John P Lazarus

Chung-Chia Chang

Gregory L Davoll

Mohamed H El-Ruby

David Wilhite

Damian Leo Osisek

David Bruce Lindquist

Jeffrey Alan Frey

Stephen James Hobson

Geoffrey Owen Blandy

Ronald M Smith

Timothy J Siegel

David B Emmes

Donald Fred Ault

Joseph M Gdaniec

Julian Thomas

David Paul Brelsford

Ronald F Hill

David Richard Page

Clark Kurtz

Jean-Louis Lafitte

Melvin M Cutler

An instruction is provided to perform invalidation of an instruction specified range of segment table entries or region table entries. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof.

Invalidating a range of two or more translation table entries and instruction therefor

Invalidating a range of two or more translation table entries and instruction therefore

An instruction is provided to perform clearing of selected address translation buffer entries (TLB entries) associated with a particular address space, such as segments of storage or regions of storage. The buffer entries related to segment table entries or region table entries or ASCE addresses. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof.

Clearing selected storage translation buffer entries bases on table origin address

Clearing selected storage translation buffer entries based on table origin address

Selected units of storage, such as segments of storage or regions of storage, are invalidated. The invalidation is facilitated by the setting of invalidation indicators located in data structure entries corresponding to the units of storage to be invalidated. Additionally, buffer entries associated with the invalidated units of storage or other chosen units of storage are cleared. An instruction is provided to perform the invalidation and/or clearing. Moreover, buffer entries associated with a particular address space are cleared, without any invalidation. This is also performed by the instruction. The instruction can be implemented in software, hardware, firmware or some combination thereof, or it can be emulated.

Invalidating storage, clearing buffer entries, and an instruction therefor

Method, system and program product for clearing selected storage translation buffer entries

Selected units of storage, such as segments of storage or regions of storage, may be invalidated. The invalidation is facilitated by the setting of invalidation indicators located in data structure entries corresponding to the units of storage to be invalidated. Additionally, buffer entries associated with the invalidated units of storage or other chosen units of storage may be cleared. An instruction is provided to perform the invalidation and clearing. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof.

Method, system and program product for invalidating a range of selected storage translation table entries

A virtual address is translated to a real address using one or more tables at varying levels. An entry of a table is indexed based in part on a table origin and a table offset. The virtual address includes one or more indexes corresponding to the one or more varying level tables. A table is addressed as a function of the table origin and the corresponding index in the virtual address. The table offset indicates the actual beginning of the table from the origin.

Table offset for shortening translation tables from their beginnings

Six instructions for the manipulation of discontinuous memory locations in a computer memory are described. They are: Compare and Load (CL), Compare and Swap (CS), Double Compare and Swap (DCS), Compare and Swap and Store (CSST), Compare and Swap and Double Store (CSDST), and Compare and Swap and Triple Store (CSTST). In each instruction a processor associates a programming-specified blocking symbol with a lock not accessible to software. The lock is used by any of these instructions only during its single instance of instruction execution, and the lock is made available (unlocked) at the end of each instance to then enable another blocking-symbol instruction instance to use the lock, thereby serializing concurrent multiple processor requests for accessing the same resource. Programming associates resources in a system with the unique blocking symbols. Each instance of these instructions executes an operand earlier prepared from a data value taken from the resource.. The data value is checked for change during the instance of execution when equality indicates no change since its preparation. These blocking-symbol instructions significantly increase the computer's speed of changing noncontiguous locations in a resource, compared to the time needed by software-protocol locks which must operate over a plurality of instances to make corresponding changes in a resource.

Method utilizing a set of blocking-symbol resource-manipulation

A method and apparatus for fully restoring the context of a user program, including program status word (PSW) and CPU register contents, following an asynchronous interrupt. Upon the occurrence of an asynchronous interrupt event, control is transferred from the normally executing part of the user program to an interrupt handler of the operating system kernel. The kernel interrupt handler saves the contents of the CPU registers and PSW as they existed at the time of the interrupt in a save area associated with the user program before transferring control to a signal catcher routine of the user program. When it has finished handling the interrupt, the signal catcher routine restores the previous state of program execution as it existed before the interrupt by storing the address of the save area in a selected register (which may be a general register/access register pair), restoring the contents of the registers other than the selected register containing the address of the save area, and then restoring the contents of the PSW and selected register by using a new Resume Program (RP) instruction. The RP instruction contains an operand field specifying through the selected register the base address of the save area together with offset fields specifying the offsets of the saved contents of the PSW and selected register relative to the beginning of the save area. Upon decoding an RP instruction, the CPU executing the instruction adds the displacement to the base address contained in the specified register to form the beginning address of the save area, to which it adds the specified offsets to access the saved PSW and selected register contents. The current PSW and selected register contents are then restored with the saved contents to fully restore the previous program context and return control to the instruction being executed at the point of interrupt. To ensure system integrity, only those fields of the PSW are restored that could have otherwise been restored by a program operating in problem state.

Method and apparatus for fully restoring a program context following an

Provides a processor method of executing instances of a Perform Locked Operation (PLO) instruction for enabling a recovery of the consistency of a resource unit being changed by a PLO instance when processor failure occurs anywhere during execution of the PLO instance. The method uses a PLO save area for each processor in a computer system capable of executing PLO instructions. Each PLO save area has a resource-inconsistency (RI) indicator having an RI state and a non-RI state, and stores the function code (FC) of the PLO instance. The RI state indicates that the resource is in a non-usable potentially inconsistent state, and the non-RI state indicates the resource is in the consistent state and may be used. A processor executing a PLO instance writes into its PLO save area all resource addresses where a change is to be made in the resource unit, and also writes in its PLO save area all operand values which will be used to change the resource at the associated addresses. After the processor has successfully written all of these addresses and associated operand data values into its PLO save area, the processor sets its RI indicator to the RI state, and then stores into the resource unit the data values stored in its PLO save area at the resource addresses also stored in its PLO save area, according to the FC also stored therein. After completing all changes in the resource, the processor sets its RI indicator to the non-RI (resource consistent) state. If the processor should ever fail while executing a PLO instance, it signals its failing condition to the system. Then, a RCR method is executed by any operational processor (acting as a RCR processor) to recover the consistency of the resource unit. The RCR method uses the state of the RI indicator with the failed processor's PLO save area, the FC stored therewith, and the content of the failed processor's PLO save area to restore the consistency of the resource unit.

Method of executing perform locked operation instructions for supporting

Provides a processor CLE (CPU lock element) for each processor in a protected storage in a multi-processor computer system. Each CLE contains a blocking symbol field (called herein a PLT, program lock token, field), a lock field H, and a wait field W which is used to chain plural CLEs currently having the same blocking symbol. When the lock field H is set to a lock held state, it indicates the associated processor has exclusive rights to access a data resource unit associated with the blocking symbol in the CLE entry. When the wait field in a lock entry contains a pointer to another lock entry and the H field in the lock entry indicates a not held state, the associated processor is waiting for the resource and cannot further execute its PLO instance until it later gets set to the lock state, which is done by the processor of the prior CLE in the chain when it completes execution of its PLO instance. Each PLO instruction also has operand fields, and a function code (FC). The FC controls the manner of processing done by the PLO instance on its operands. Blocking symbols are specified by software to enable the software to utilize hardware enforced serialization of multi-processor accesses simultaneously requested for accessing the same data resource in the computer system. The plural processors may simultaneously, and at any time, initiate PLO instances for the same or different blocking symbols. When different processors simultaneously execute PLO instances having different blocking symbols, the processors may execute in parallel without conflict. But if the different processors simultaneously execute PLO instances having the same blocking symbol, the processors cannot execute in parallel without potential conflict, and the processors must serialize the execution of their PLO instances for accessing the same resource. In the latter case, their CLEs are chained through pointers in wait fields of the CLEs.

Processor associated blocking symbol controls for serializing the

PLO (perform locked operation) instructions containing blocking symbols are executed on each of multiple processors in a computer system to control coherence in data structures which may be changed by any of multiple processors in a computer system. The blocking symbol is extracted from a PLO instruction instance when invoked by its executing processor. Then the processor hashes the blocking symbol using hardware-microcode (H-M) to generate the location of a lock field in protected storage. The PLO instruction's blocking symbol is associated with a computer resource unit by software providing the PLO instruction, and the blocking symbol then associates the resource with a protected lock through the hashing operation on the blocking symbol. A processor must obtain the lock for a blocking symbol before the executing PLO instruction instance is allowed to make access and change the resource unit associated with the blocking symbol. The blocking symbol controls the PLO operations by serializing simultaneously PLO instruction access requests being made by multiple processors to the same resource unit using the same blocking symbol to allow only one PLO instruction instance to have exclusive access to the resource at a time.

Blocking symbol control in a computer system to serialize accessing a

Provides data and program integrity in a computer system by guarding against malicious program operation when using the Branch In Subspace Group instruction (BSG) of the S/390 computer architecture. System integrity is ensured by providing a controlled target space (a base space) and branch address during a BSG transfer of control (branch) from a subspace, and a different PSW key mask (PKM) for the base space than for subspaces. More specifically, (1) the PKM is reduced and a new PSW access key is set during a BSG branch from the base space to a subspace, (2) the original PKM and access key and also a return address are saved in a secure data area during the same branch, and (3), during a branch from a subspace, the original PKM and access key are restored, and the branch is made to the return address (the controlled branch address) in the base space. The method is extended to apply to a single address space by a novel Branch and Set Authority instruction (BSA) that, when executed in a base-authority state, saves a return address and base authority in a secure data area and sets a reduced-authority state; and, when executed in the reduced-authority state, branches to the saved return address, restores the saved base authority, and sets the base-authority state.

Authority reduction and restoration method providing system integrity

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Poughkeepsie, NY, United States of America

Kenneth E Plambeck