Rockwell International Corporation

Skyworks Solutions, Inc.

Conexant Systems, Inc.

Maxim Integrated Products, Inc.

Kenneth E Garey

Keith M Bindloss

John S Walley

John Earle

Ganning Yang

George A Watson

Ricke Waylan Clark

Kaveh Razazian

Mark E Miller

Victor Loginov

Afshin Niktash

Doug Berger

Stephen C Muller

Bhasker P Patel

Lawrence F Blank

A power line communication (PLC) system includes a source node, a plurality of intermediate nodes and a destination node. Each of the source node, the plurality of intermediate nodes and the destination node comprise a PLC interface including a medium access control (MAC) module and a physical layer (PHY) module. A transformer is located between the source node and the destination node. Routing modules of the source node, one or more of the intermediate nodes, and the destination node establish a route from the source node to the destination node via one or more selected ones of the plurality of intermediate nodes. The route is selected using a route cost that is calculated based on link costs of a plurality of hops in the route from the source node to the destination node. The link costs are based on forward link costs and reverse link costs.

Routing for power line communication systems

A communication device that includes a base. The base includes a line interface for receiving incoming communications over a network line and sending outgoing communications over the network line, a communication transceiver for interfacing the communication device over a communication link to other communication devices in a same in-home network and for interfacing other communication devices in the same in-home network to the line interface via the communication link, and a storage medium for storing communication software that allows the communication device to communicate with other communication devices through the transceiver. The communication device also includes a processor coupled to the storage medium and to the line interface. The processor is configured to run the communication software and to receive incoming communications through the line interface and to send an outgoing communications through the line interface. The communication transceiver can be a RF short range transceiver.

Efficient and flexible communication device and system with base-to-base communication

A full-duplex speakerphone that is coupled to a network such as the public switched telephone network. The full-duplex speakerphone includes a base station, which has a network connection and receives a network signal from the network. The base station also includes a speaker for audibly outputting a signal derived from the network signal into a room in which the speakerphone is located. The base station also includes a wireless receiver for receiving signals transmitted over the air from a wireless remote microphone equipped with a wireless transmitter, the received signals being sent by the base station over the network.

Full-duplex speakerphone with wireless microphone

An apparatus and method for recording at least two separate incoming signals which reduces computational complexity and memory requirements of the recording device. In one embodiment, the apparatus records and stores the first arriving signal using a high-compression algorithm to reduce memory requirements. Upon receipt of a second signal concurrent with the first arriving signal, the apparatus records and stores the second signal using a second compression algorithm with a lower compression ratio. The second algorithm requires less hardware or processor resources while still providing a moderate degree of compression in relation to the first algorithm. Upon completion of receipt of the first arriving signal, the second signal which was compressed using the second algorithm is decoded and then re-encoded using the first high-compression algorithm. This further reduces memory storage requirements without requiring additional hardware or processor capability. It is contemplated that one embodiment of the subject invention comprise a two line telephone answering machine.

Multi-line recording device having reduced processing and storage requirements

A signal processor that contains a programmable logic circuitry that is re-configurable in response to various parameters including, but not limited to, characteristics of a plurality of input data that is provided to the signal processor. The signal processor contains, among other things, a programmable logic configuration circuitry that provides a logic configuration to the programmable logic circuitry. In certain embodiments of the invention, the signal processor employs a wide word width to program the programmable logic circuitry, the wide word width is operable to configure an entirety of the programmable logic circuitry. The programmable logic configuration circuitry further contains a default configuration circuitry and an adaptive configuration circuitry. The default configuration circuitry contains a default logic configuration for the programmable logic circuitry. In other embodiments of the invention, the adaptive configuration circuitry generates an adaptive logic configuration for the programmable logic circuitry. The programmable logic circuitry is partitioned into a plurality of areas, each area within the plurality of areas is independently programmable.

Method and apparatus of selecting one of a plurality of predetermined configurations using only necessary bus widths based on power consumption analysis for programmable logic device

A bidirectional communication device for transmitting and receiving communications signals in a system which presents a transmission path for conducting a communications signal from the device, a reception path for conducting a communications signal to the device, and an echo path which conducts echo signals from the transmission path to the reception path, the device having an echo canceler connected between the transmission path and the reception path for minimizing echo signals in the transmission path, the echo canceler comprising an adaptive filter for filtering the communications signals from the device according to a filter characteristic having a plurality of filter coefficients, wherein a first group of the coefficients, constituting less than all of the coefficients, has finite filter coefficient values and the remaining ones of the plurality of coefficients have values of zero.

Echo canceling method and apparatus in a communication device

The AGC circuit and method especially applicable in circuits where fast response and stability of the system is necessary, such as where input signals are speech patterns. A gain feedback loop repeatedly adapts the gain and a long term average energy E.sub.mean of the output signal until it approaches a predetermined level. In each pass through the gain feedback loop the long term average energy E.sub.mean is increased by a gain compensation parameter directly proportional to a gain change, thereby rapidly adapting the long term average energy E.sub.mean to converge to the predetermined level.

Method and apparatus for automatic gain control with improved response

A data processing apparatus having a pipeline computer architecture with an input pipeline latch is disclosed. The data processing apparatus includes an ALU that executes a plurality of processing instructions. At least some of the instructions have an immediate data format including a field for intermediate data and a field for specifying a destination for an output. The ALU uses two operands for performing at least some of the instructions having the immediate data format. The ALU conditionally accepts either the contents of the input pipeline latch or the ALU output of the previous instruction as a second operand to an immediate instruction depending on the destination specified in the destination field of the previous instruction.

Microprocessor system with flexible instruction controlled by prior

A signal indicating the quality of the received digital data in an ADPCM cordless telephone system is monitored and a transition from good to poor quality is detected. In response to this detection, a first attenuation level is applied to the received signal, the level being selected to maintain the intelligibility of the signal to the user while lowering the volume thereof. The first attenuation level is then reduced such that reduced attenuation is maintained over a time interval selected to accommodate for the known error propagation time of the ADPCM signal. An optional clipping circuit may be employed to limit the excursion of the output audio signal.

Audio mute for digital cordless telephone

A space vector data path for integrating SIMD scheme into a general-purpose programmable processor. The programmable processor uses a mode field in each instruction to specify, for each instruction, whether an operand is processed in either one of vector or scalar modes. The programmable processor also has a plurality of sub-processing units for receiving the operand and, responsive to an instruction as specified by the mode field in each instruction, for processing the operand in either one of the vector or scalar modes, wherein the vector mode indicates to the plurality of sub-processing units that there are a plurality of elements within the operand and the scalar mode indicates to the plurality of sub-processing units that there is but one element within the operand. For the vector mode, each element is processed by one of the sub-processing units concurrently to generate a vector result. For the scalar mode, the sub-elements of the one element operand are processed by the sub-processing units concurrently but independently to generate a scalar result.

Space vector data path

The STREAMER FOR RISC DIGITAL SIGNAL PROCESSOR shown herein allows a CPU 46 to interface with a memory 60 via data registers 50. Pre-fetch and post-store of the correct address is determined by an address generator 58 according to a rule determined by a context register 52. An index indicative of this address is stored in an index register 54. The data, context, and index registers together form a streamer 56, streaming data between the CPU 46 and data memory 60. The rule of the context register 52 also drives a converter 62 for converting data between memory format and register format. The speed and flexibility of a RISC device is combined with the intensive memory access of a digital signal processor.

Triple register RISC digital signal processor

The signal processor including a CPU 10 which selects a context register 16, the contents of which configure an address generator 20 and a data type converter 22. A narrow parameter from the CPU 10 produces a broad address for the generator 20 to pass to the memory 28. The converter 22 converts data between memory 28 format and CPU 10 format. A different context register 16 may be selected by each code line of software. The generator 20 preferably calculates a data element length which is the product of an odd number and a power of two, each number being specified in the content of the Context Register 16. Elements are clustered into groups, one group for each element length, and the groups are arranged in order of ascending element length. The index identifying the individual element of a group with a larger element length does not begin with zero (or one). Instead, the lowest index used is sufficiently large that the memory space which would have been occupied with lower indexed elements may instead be occupied by the groups of smaller element lengths.

Growing community of inventors

Irvine, CA, United States of America

Kenneth E Garey