Honeywell Information Systems Inc.

Bull Hn Information Systems, Inc.

Honeywell Bull, Inc.

Kenneth E Bruce

John W Conway

Ralph M Lombardo, Jr

Bruce H Tarbox

John J Bradley

George J Barlow

Thomas O Holtey

David B O'Keefe

Gary J Goss

James W Keeley

Chester M Nibby, Jr

Richard C Zelley

A central subsystem of a data processing system includes a writable control store which is loaded with firmware to control the central subsystem operations. The central subsystem logic is responsive to a sequence of commands from a system management facility to load the control store and verify that the control store firmware is loaded correctly.

Apparatus for loading and verifying a control store memory of a central

A display subsystem having a graphics capability includes a bit map memory for storing bits, each bit representing a displayed pixel. A read only memory stores words, each word representative of a pixel of a selected pattern which is used to fill out an area of the display thereby clearly identifying adjacent areas of the display to the operator. The selected patterns are displayed in a REPLACE, an OR or an EXCLUSIVE OR mode of operation.

Pattern generation for a graphics display

The invention pertains to a method and apparatus to provide for the display of characters and graphics in color. The invention includes three bit map memories which store graphics information for different colors, one character generator driven from a text memory for display of text, and an attribute memory for storing display characteristics such as inverse video and blinking. The contents of the bit map and attribute memories and the output of the character generator are used to address a pre-programmed ROM. The output from the ROM is a string of three bit words with each bit stream representing a primary color on a color CRT and being connected to the associated color input to the CRT. Composite graphics and text are displayed on the CRT.

Computer display system for producing color text and graphics

A graphics display is cleared by apparatus forcing binary ZERO's into all locations of the bit map memories between successive vertical synchronization operations during a write refresh operation.

Apparatus for distortion free clearing of a display during a single

A color display graphics system includes three bit map memories for storing bits representing red, green and blue colors respectively. Combinations of bits from the same address locations of each bit map memory display a pixel which could be any one of eight colors: black, blue, green, cyan, red, magenta, yellow or white. A read only memory (ROM) stores patterns made up of sixteen bits in a four-by-four matrix for each of the red, green and blue colors. The 16-bit matrices are stored in their respective bit map memories for subsequent color display. Combinations of matrices may be used to show shades of the above eight colors and the mixing of any of those shades.

Multiple color generation on a display

The invention pertains to a computer display system for displaying text and graphics on a scan line basis wherein a scan line windowing apparatus for selectively blanking the graphics display is provided. A bit map memory, in addition to storing information to be displayed on a CRT, further stores a bit for each scan line which is utilized to control the enabling or disabling of a portion of the information in the bit map memory which is to be displayed on the CRT.

Graphic display scan line blanking capability

An error detection system is disclosed for not only indicating but eliminating certain errors which may occur during the transfer of information between communication busses in a data processing system wherein plural communication busses each provide a common information path to plural data processing units including memory units, peripheral control units, central processing units and ISL units, and wherein each of the plural communication busses are in electrical communication with an ISL unit, and ISL units are electrically connected in pairs. The error detection system requires no special supporting software or firmware on the part of any data processing unit on any of the communication busses.

Intersystem fault detection and bus cycle completion logic system

A logic system is provided for accommodating the exchange of information between two or more communication busses of a data processing system, wherein plural central processing units and plural memory units on independent communication busses may have same logic addresses. Memory and CPU addresses are translated at the bus rate through a multiplicity of flexible address translation ranges to enable a data processing unit on one communication bus to access an apparent contiguous range of addresses encompassing all data processing units on all communication busses.

Intersystem translation logic system

An intersystem communication control system in an intersystem link (ISL) unit is provided to accommodate the simultaneous bidirectional transfer of binary coded information between communication busses in a data processing system, wherein the plural communication busses are electrically interconnected by ISL unit twins, and information may be transferred between plural communication busses asynchronously.

Asynchronous multi-communication bus sequence

A logic control system in an intersystem link (ISL) unit accommodating the transfer of binary coded information between communication busses in a data processing system is disclosed, wherein information may be transferred between plural communication busses while further information flow continues on each communication bus at the bus rate, and additional information transfers between the communication busses continue to be handled by the ISL unit.

Intersystem cycle control logic

A logic control system in an intersystem link (ISL) unit accommodating the transfer of binary coded information between communication busses in a data processing system is disclosed, wherein an ISL unit may be reconfigured to reallocate communication bus resources without incurring excessive software overhead time losses.

Logic system for selectively reconfiguring an intersystem communication

A logic system in an intersystem link (ISL) unit accommodating the transfer of binary coded information between communication busses in a data processing system is disclosed, wherein dedicated locations in a file register are selected at the bus rate in response to binary coded information received from a local communication bus. ISL transactions to be initiated in response to bus cycle requests thereby are identified. ISL transactions are handled in parallel, and memory transfers are segregated from non-memory transfers to avoid unnecessary delays in memory transfers.

Intersystem transaction identification logic

A logic control system is disclosed for verifying the operability of memory and non-memory data and control paths in both local and remote intersystem link (ISL) units electrically interconnecting a local and remote communication bus in a data processing system. The data processing system may include two or more communication busses each pair of which are electrically interconnected by twin ISL units. The control logic architecture accommodates the receipt of a test mode command from a CPU on a local bus to initiate a test mode operation wherein the memory and non-memory data and control paths of both the local and the remote ISL units are excerised while on-line, and binary coded information received from the local bus is passed through the ISL units, onto the remote bus, and returned to a local bus memory resource for verification. No remote bus resources are used or affected, and the remote ISL unit shall ignore any communications received from any other data processing unit on the remote bus. The remote ISL unit is effectively non-existent to other data processing units on the remote bus.

Test mode control logic system

A logic system referred to as an intersystem link unit (ISL) is provided for accommodating the transfer of binary coded information between two or more communication busses in a data processing system, wherein information including memory and non-memory read and write requests, CPU to CPU interrupts, peripheral control units to CPU interrupts may be transferred between plural communication busses each supporting plural data processing units including plural CPUs without substantially affecting the bus rate of the individual communication busses. Binary coded information from a communication bus is acquired asynchronously, and plural bus communications of different types are accommodated in parallel. The ISL units further may be dynamically reconfigured to provide for a reallocation of communication bus resources between communication busses.

Intersystem communication link

A logic system in an intersystem link (ISL) unit is provided for avoiding deadlock conditions which may occur in a data processing system wherein multiple CPUs on one communication bus attempt to communicate with resources on remote communication busses. The data processing system has plural communication busses, each providing a common information path to plural data processing units including memory units, peripheral control units, central processing units (CPUs) and ISL units, and each of the plural communication busses are in electrical communication with an ISL unit, and ISL units are electrically connected in pairs.

Growing community of inventors

Nashua, NH, United States of America

Kenneth E Bruce