International Business Machines Corporation

Kenneth E Beilstein, Jr

Claude Louis Bertin

Wayne John Howell

James Marc Leas

John Edward Cronin

David J Perlman

Timothy Harrison Daubenspeck

Christopher P Miller

Jack Allan Mandelman

Francis Roger White

Harish N Kotecha

Edmund Juris Sprogis

Gordon A Kelley, Jr

Gustav Schrottke

Gordon Arthur Kelley

Robert B Phillips, Iii

Jody John VanHorn

Dennis Charles Dubois

John Atkinson Fifield

Howard L Kalter

Dale E Pontius

Lawrence G Heller

Hsing-San Lee

Willem B Van Der Hoeven

John R Pessetto

Charles H Stapper

Steven Platt

Methods and apparatus are set forth for burn-in stressing and simultaneous testing of a plurality of semiconductor device chips laminated together in a stack configuration to define a multichip module. Testing is facilitated by connecting temporary interconnect wiring to an access surface of the multichip module. This temporary interconnect wiring electrically interconnects at least some semiconductor device chips within the module. Prior to burn-in stressing and testing, a separate electrical screening step occurs to identify any electrical defect in the connection between the temporary interconnect wiring and the multichip module. If an electrical defect is identified, various techniques for removing or isolating the defect are presented. Thereafter, burn-in stressing and simultaneous testing of the semiconductor chips within the multichip module occurs using the temporary interconnect wiring. Various alignment and test fixtures are described for facilitating this burn-in and simultaneous testing of the semiconductor chips within the multichip module.

Methods and apparatus for burn-in stressing and simultaneous testing of

A method of forming a sub-lithographic image formed by the intersection of two spacers. A substrate with a first pattern of selectively etchable material with sidewalls that are substantially vertical is provided. A first sidewall spacer is formed of a material that is selectively etchable relative to the first pattern material. A second pattern of a selectively etchable material is formed with the second pattern intersecting the first pattern. The sidewalls of the second pattern are substantially vertical as well. A second sidewall spacer is formed of a material that is selectively etchable relative to the second pattern material. The second pattern material is etched to leave the second sidewall spacer. Alternatively, the first and/or second pattern materials may be totally removed, left in place, or planarized

Structure for making sub-lithographic images by the intersection of two

A method of forming a sub-lithographic image formed by the intersection of two spacers. A substrate with a first pattern of selectively etchable material with sidewalls that are substantially vertical is provided. A first sidewall spacer is formed of a material that is selectively etchable relative to the first pattern material. A second pattern of a selectively etchable material is formed with the second pattern intersecting the first pattern. The sidewalls of the second pattern are substantially vertical as well. A second sidewall spacer is formed of a material that is selectively etchable relative to the second pattern material. The second pattern material is etched to leave the second sidewall spacer. Alternatively, the first and/or second pattern materials may be totally removed, left in place, or planarized.

A fabrication method including a semiconductor chip kerf clear process and a resulting semiconductor chip and electronic module formed thereby. The fabrication method includes providing a wafer comprising a plurality of integrated circuit chips having kerf regions between them. Chip metallization is present within the kerf regions. A photolithography process is used to protect the wafer exposing only the kerf regions. Next, the wafer is etched, clearing the chip metallization from the kerf regions. The wafer is then diced and the chips are stacked to form a monolithic electronic module. A side surface of the electronic module is processed to expose transfer metals extending thereto, thereby facilitating electrical connection to the chips within the electronic module. Specific details of the fabrication method, resulting integrated circuit chips and monolithic electronic module are set forth.

Semiconductor chip kerf clear method for forming semiconductor chips and

A fabrication method and resultant monolithic electronic module having a separately formed thin-film layer attached to a side surface. The fabrication method includes providing an electronic module composed of stacked integrated circuit chips. A thin-film layer is separately formed on a temporary support which is used to attach the thin-film layer to the electronic module. The disclosed techniques may also be used for attaching an interposer, which may include active circuity, to an electronic module. Specific details of the fabrication method, resulting multichip packages, and various thin-film structures are set forth.

Method and workpiece for connecting a thin layer to a monolithic

Method for making sub-lithographic images by etching the intersection of

Semiconductor chip kerf clear method and resultant semiconductor chip

A three-dimensional five transistor SRAM trench structure and fabrication method therefor are set forth. The SRAM trench structure includes four field-effect transistors ('FETs') buried within a single trench. Specifically, two FETs are located at each of two sidewalls of the trench with one FET being disposed above the other FET at each sidewall. Coaxial wiring electrically cross-couples the FETs within the trench such that a pair of cross-coupled inverters comprising the storage flip-flop for the SRAM cell is formed. A fifth, I/O transistor is disposed at the top of the trench structure, and facilitates access to the flip-flop. Specific details of the SRAM trench structure, and fabrication methods therefor are also set forth.

Three-dimensional SRAM trench structure and fabrication method therefor

Semiconductor chip having chip metal layer and transfer metal layer

This invention comprises various high production methods for simultaneously forming surface metallizations on a plurality of monolithic electronic modules. Each monolithic electronic module may comprise a single semiconductor chip or multiple semiconductor chips. The methods can employ a workpiece which automatically discontinues side surface metallization between different electronic modules in the stack. Multiple workpieces are interleaved within the stack between the electronic modules. Each workpiece may include a transfer layer(s) for permanent bonding to an end surface of an adjacent electronic module in the stack. This transfer layer may comprise an insulation layer, a metallization layer, an active circuit layer, or any combination thereof. End surface metallization can thus be provided contemporaneous with side surface metallization of multiple electronic modules.

Monolithic electronic modules--fabrication and structures

Semiconductor chip having a chip metal layer and a transfer metal and

Fabrication processes for monolithic electronic modules

Growing community of inventors

Essex Junction, VT, United States of America

Kenneth E Beilstein, Jr