Texas Instruments Corporation

Kenneth E Bean

Satwinder S Malhi

David B Spratt

Eldon J Zorinsky

Robert L Virkus

Richard L Yeakley

William W Lloyd

Robert H Havemann

Richard A Chapman

Pallab K Chatterjee

Chi-Cheong Shen

Francois A Padovani

Douglas P Verret

Walter T Matzen

Satwinder D Malhi

Don Leslie Kendall

Andrew P Lane

Robert Daniel McGrath

John Powell

Jack W Freeman

Ronald K Smeltzer

Peng-Heng Chang

Charles C Driscoll

Walter R Runyan

A semiconductor wafer (32) is patterned to have gettering areas (36-38) selectively positioned proximate devices (44-46) which require gettering. The areas (36-38) comprise germanium-doped silicon having a germanium concentration of approximately 1.5%-2.0%. The germanium creates a lattice mismatch between the substrate (32) and an epitaxial layer (34) which is sufficient to produce defects capable of gettering contaminants. The gettering areas (36-38) may be formed by selective deposition, selective etching, ion-implantation or selective diffusion techniques.

Discretionary gettering of semiconductor circuits

The invention relates to a method of scribing and separating dice from each other after fabrication in a semiconductor wafer in a manner such that active circuit regions in the dice reside as near to an edge of a die as possible. The wafer is anistropically etched through the active layer and into the substrate through an opening in the mask to form a generally V-shaped channel with the dice then being separated along a vertex of the channel. The dice are then positioned to abut each other in the form of a mosaic.

Method of fabricating an integrated circuit having active regions near a

A method for preparing a germanium layer (22) adjacent to a germanium silicon layer (20). Initially, a P-germanium silicon layer (16) is deposited on to an N-germanium silicon layer (14). The continuous germanium layer (22) is formed by heating the layers (14 and 16) in a steam oxidation step to approximately 1000 degrees Centigrade to transform the P-germanium silicon layer (16) into the P-germanium layer (18) and a SiO.sub.2 layer (22). A method for forming a heterojunction bipolar transistor utilizing a P-germanium layer (50) is also disclosed.

Method for forming a germanium layer and a heterojunction bipolar

A baseboard for orthogonal mounting of integrated circuit chips thereto is described. Plural channels (14) are anisotropically etched in a silicon baseboard (10). A corresponding plurality of integrated circuit chips (12) are inserted into the channels (14). A number of baseboard contact pads (18) are formed adjacent each channel (14), and are solder bonded to corresponding chip conductor pads (16). Interconnect conductors (20, 28) provide connection of each baseboard pad (18) either to other chips (12) or to connector pads (22) located adjacent an edge (26) of the baseboard chip mount (10). A coating (30) of silicon carbide over the surface of the baseboard chip mount (10) improves the thermal efficiency of the assembly.

Baseboard for orthogonal chip mount

A silicon on insulator semiconductor structure employs a strain layer fabricated of an electrically inactive material. The strain layer comprises silicon with a germanium additive to produce a sublayer exhibiting a low breakdown voltage and thus effective for selective anodization.

Anodizable strain layer for SOI semiconductor structures

A baseboard for orthogonal mounting of integrated circuit chips is described. Plural channels (14) are anisotropically etched in a silicon baseboard (10). A corresponding plurality of integrated circuit chips (12) are inserted into the channels (14). A number of baseboard contact pads (18) are formed adjacent each channel (14), and are solder bonded to corresponding chip conductor pads (16). Interconnect conductors (20, 28) provide connection of each baseboard pad (18) either to other chips (12) or to connector pads (22) located adjacent an edge (26) of the baseboard chip mount (10). A coating (30) of silicon carbide over the surface of the baseboard chip mount (10) improves the thermal efficiency of the assembly.

Preferred embodiments include silicon-on-insulator structures (30) and integrated circuits include a thin single crystal silicon layer (32) on a silicon dioxide layer (34) which is on a polysilicon layer (36) bonded to a surface-oxidized silicon substrate (42) by a glass layer (38). Also, single crystal silicon layers on oxide on polysilicon substrates and methods of fabrication are included in the preferred embodiments.

Silicon-on-insulator integrated circuits and method

An orthogonal chip mount system module (10) comprising a base module (12), an interconnect chip (14), orthogonal slots (16) and semiconductor chips (18) is provided. The interconnect chip (14) is fixed to the base module (12) by high thermal conductivity epoxy. The semiconductor chips (18) are interference fitted into the slots (16). Solder pads (20) on the semiconductor chips (18) are aligned with solder pads (22) on the interconnect chip (14) and the system module (10) is then heated to the reflow temperature of the solder forming joints (24).

Orthogonal chip mount system module and method

The disclosure relates to a three dimensional semiconductor structure formed in a semiconductor substrate wherein electrical components, both active and passive, are formed on the substrate surface as well as in grooves formed in the substrate at an angle and extending to the surface. The substrate surface is designed to lie in a predetermined crystallographic plane of the substrate material and the grooves extend in a predetermined crystallographic direction from said plane, this being accomplished by orientation dependent etching.

Method of making three dimensional structures of active and passive

Three dimensional structures of active and passive semiconductor

The disclosure relates to a method of growing thermal oxide on silicon wherein the oxide is grown at an increased rate, at reduced temperature or a combination thereof. This is accomplished by operating in an hermetic quartz tube capable of withstanding high pressure with steam or oxygen at super atmospheric pressure.

Semiconductor processing facility for providing enhanced oxidation rate

Disclosed are improved field-effect and bipolar semiconductor devices and the method of making them, wherein maximum junction control provides highly predictable device parameters. Low temperature epitaxial depositions provide tight junction thickness and resistivity control, and an orientation dependent etch forms grooves circumscribing portions of the host substrate and overlying epitaxial layers to provide dielectrically isolated single crystalline mesas utilized in forming electronic devices.

FET and bipolar device and circuit process with maximum junction control

This disclosure relates to methods of producing thin layers of silicon as well as thin layers of silicon on insulating substrates such as silicon dioxide or polycrystalline silicon by forming either an n- layer of single crystal silicon over a p++ layer of single crystal silicon or a p- layer of single crystal silicon over an n++ layer of single crystal silicon and then removing either the n++ or p++ single crystal substrate, as the case may be, by utilizing an etch which will only etch the n++ or p++ region and will stop when the n- or p- region, as the case may be, has been reached.

Process for thinning silicon with special application to producing

This disclosure defines an infrared image detector formed in a block of semiconductor material by etching slots in the semiconductor material. The slots define the individual detectors, effectively isolate them from each other both optically and electrically, and permit the detectors to be placed very close to each other.

Growing community of inventors

Richardson, TX, United States of America

Kenneth E Bean