Goodyear Aerospace Corporation

Loral Corporation

Kenneth E Batcher

A technique for laying out large multistage interconnection networks. The invention provides for the division of a network into sub-networks which may be maintained on printed circuit boards and then provides for the addition of switching circuitry at the inputs or outputs of such boards such that pin locations on the boards may be swapped with each other to allow for a parallel interconnection of corresponding pins between the boards. Such parallel interconnection eliminates the existence of rat's nests in the wiring harness.

Layout of large multistage interconnection networks technical field

The invention herein relates to a computer organization capable of rapidly processing extremely large volumes of data. A staging memory is provided having a main stager portion consisting of a large number of memory banks which are accessed in parallel to receive, store, and transfer data words simultaneous with each other. Substager portions interconnect with the main stager portion to match input and output data formats with the data format of the main stager portion. An address generator is coded for accessing the data banks for receiving or transferring the appropriate words. Input and output permutation networks arrange the lineal order of data into and out of the memory banks.

Staging memory for massively parallel processor

A processing element constituting the basic building block of a massively-parallel processor. Fundamentally, the processing element includes an arithmetic sub-unit comprising registers for operands, a sum-bit register, a carry-bit register, a shift register of selectively variable length, and a full adder. A logic network is included with each processing element for performing the basic Boolean logic functions between two bits of data. There is also included a multiplexer for intercommunicating with neighboring processing elements and a register for receiving data from and transferring data to neighboring processing elements. Each such processing element includes its own random access memory which communicates with the arithmetic sub-unit and the logic network of the processing element.

Processing element for parallel array processors

The invention relates to a unique solid state computer organization. Essentially, the system comprises a plurality of associative arrays wherein each associative array comprises parallel processing apparatus and a solid state memory capable of being accessed in either a word-oriented or a bit-oriented mode. The associative processor apparatus within each associative array provides for the parallel processing of data within the associative arrays in either of the two modes. Control apparatus within the system provides for the parallel control of the plurality of associative arrays at a speed conducive to the data processing speed of the associative arrays. Rapid speed of the control apparatus is economically achieved by the arrangement of a plurality of separate and characteristically distinct control memory elements.

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Stow, OH, United States of America

Kenneth E Batcher