Qualcomm Incorporated

Kenneth David Easton

Peter J Black

Jeffrey Alexander Levin

Roberto Padovani

Noam A Ziv

Nicholas K Yu

John Edward Smee

Fuyun Ling

Jilei Hou

Rashid Ahmed Akbar Attar

Brian K Butler

Lindsay A Weaver, Jr

Adam Edward Newham

Jurg K Hinderling

Arthur James Neufeld

Chunlei Shi

Giby Samson

Kendrick Hoy Leong Yuen

Yu Pu

Raghu Sankuratri

Christian Oliver Thelen

Senthilkumar Sundaram

Rohan Salvi

James Krysl

Peter John Black

David E Werner

Michael P Brock

Aspects relate to provision of a control message, such as an extension data section, that includes an indication of the repeat of highest priority data sections. The control message may be generated in a distributed unit (DU) and conveyed to a radio unit (RU) via a fronthaul link. The control message may include either a flag or bits in a field of an extension data section allowing a RU to determine repeat of the highest priority data section based on reception of the flag or processing of the bit value in the field. Additionally, the indication of repetition of the highest priority section may be based on a section identifier transmitted by a DU, wherein an RU receiving the section identifier may determine repeat of the highest priority data section by tracking the received section identifier.

Optimized handling of high priority data sections in a communication system

A power management system for stack memory thread tasks according to some examples of the disclosure may include a non-collapsible memory region, a collapsible memory region configured below the non-collapsible memory region, a memory management unit in communication with the non-collapsible memory region and the collapsible memory region, the memory management unit operable to allocate a portion of the non-collapsible memory region and a portion of the collapsible memory region to a thread task upon initialization of the thread task and power down the portion of the collapsible memory region allocated to the thread task upon receiving a power down command.

Systems and methods for implementing power collapse in a memory

A switchable supply network for powering multiple digital islands. In one embodiment, a first digital island includes a first power collapsible circuit and a first retention circuit, and a second digital island includes a second power collapsible circuit and a second retention circuit. In a normal mode of operation, the first digital island is provided a first supply voltage and a second digital island is provided a second supply voltage higher than the first supply voltage. In a transition mode the second power collapsible circuit is powered down and the second supply voltage is lowered and provided to the second retention circuit. When the second supply voltage falls below the first supply voltage, the first power collapsible circuit is powered down. The second supply voltage is now provided only to the retention circuits, and is furthered lowered in a retention mode to a final retention voltage.

Area and power efficient switchable supply network for powering multiple digital islands

A method and system for reverse link interference cancellation. One method comprises demodulating and decoding at least one signal sent from at least one access terminal and received by a first base station, sending demodulated, decoded information of the signal to a second base station, reconstructing the signal at the second base station, and subtracting the reconstructed signal from a buffer at the second base station.

Reverse link interference cancellation

A receiver unit includes a first buffer that receives and stores digitized samples at a particular sample rate and a data processor that retrieves segments of digitized samples from the first buffer and processes the retrieved segments with a particular set of parameter values. The data processor is operated based on a processing clock having a frequency that is (e.g., ten or more times) higher than the sample rate. Multiple instances of the received signal can be processed by retrieving and processing multiple segments of digitized samples from the first buffer. The receiver unit typically further includes a receiver that receives and processes a transmitted signal to provide the digitized samples and a controller that dispatches tasks for the data processor. The data processor can be designed to include a correlator, a symbol demodulation and combiner, a first accumulator, and a second buffer, or a combination thereof. The correlator despreads the retrieved segments of digitized samples with corresponding segments of PN despreading sequences to provide correlated samples, which are further processed by the symbol demodulation and combiner to provide processed symbols. The second buffer stores the processed symbols, and can be designed to provide de-interleaving of the processed symbols.

Method and apparatus for processing a received signal in a communications system

A technique for activating an active-mode high frequency clock following a sleep period for use within a mobile station wherein selected components of the mobile station operate using a low power, low frequency sleep-mode clock during the sleep period and the faster high frequency active-mode clock during non-sleep periods. In one embodiment, the technique is implemented by a device having a wake-up estimation unit for estimating a wake up time using the sleep-mode clock and a frequency drift compensation unit for compensating for any error in the estimated wake up time caused by frequency drift in the sleep-mode clock. An off-set time compensation unit is also provided for compensating for a lack of precision in the low frequency sleep-mode clock resulting in a possible error in the estimated wake up time. The lack of precision can result in an initial timing off-set error at the beginning of the sleep period and an final timing off-set error at the end of the sleep period. Both the frequency drift compensation unit and the off-set time compensation unit employ a high frequency transition-mode clock signal for use in calculating the time required to adjust the wake-up time. The transition-mode clock, which may have the same frequency as the active-mode clock, is employed only at the beginning and end of the sleep period and is deactivated throughout most of the sleep period to reduce power consumption.

Method and apparatus for activating a high frequency clock following a sleep mode within a mobile station operating in a slotted paging mode

The present invention is an improved method and circuit for reducing the amount of time a mobile receiver spends in the active phase of a slot in a communications system utilizing a slotted paging mechanism. The invention allows the awake time to be configured for the minimum interval needed to demodulate the paging channel messages of interest. The invention includes a means to adjust the timing reference of the fingers to compensate for a sleep duration not an integral multiple of the PN sequence period, and a means to adjust the deinterleaver frame reference timing to compensate for a sleep duration not an integral multiple of the frame interval, and a means to initialize the frequency tracking, gain scaling, and DC bias loops, if any, of the analog receiver chain to minimize the time needed to re-lock these loops.

Technique for reduction of awake time in a wireless communication device utilizing slotted paging

Coherent detection of high-speed digital wireless communications becomes more difficult when the frequencies of the transmitter and receiver oscillators do not coincide. A frequency-locked loop may be used to characterize this frequency offset by processing the samples received on a pilot channel. Rather than using the offset information thus derived to correct the frequency of the received signal, the invention realizes a considerable computational savings by applying a frequency correction to the despread pilot samples instead.

Method and apparatus for frequency offset correction

A method and circuit for controlling a mobile station operating in a slotted paging environment. The circuit comprises a low power clock for generating a low frequency clock signal; a clock signal generator for generating a high frequency clock signal; a synchronization logic circuit for synchronizing the low frequency clock signal to the high frequency clock signal; a frequency error estimator for measuring an estimated low frequency clock error; and a sleep controller for removing power from the clock signal generator for the corrected sleep duration value, thereby conserving power between assigned paging slots. During the awake time, the low frequency clock signal is resynchronized to the high frequency clock, thereby correcting for any frequency error in the less accurate low power clock during sleep mode.

Synchronization of a low power oscillator with a reference oscillator in a wireless communication device utilizing slotted paging

The finite impulse response (FIR) filter is implemented as a table using read-only memory (ROM). The FIR filter table stores a pre-calculated output filter value for each permissible combination of input values to be filtered. Streams of input values are successively shifted into the table and corresponding output values are successively output. In an exemplary implementation, the FIR filter is employed within a digital cellular telephone for use in smoothing a digital signal to be transmitted. The size of the required FIR filter table is minimized by exploiting constraints imposed upon the signal to be filtered and by exploiting linearity and symmetry within the filter itself. More specifically, the telephone employs a data burst randomizer to provide a data signal composed of sequences of null or 0 values and sequences of antipodal values (+1's and -1's). Hence, the permissible input combinations for the FIR filter include only patterns containing either all antipodal signals, all null signals, leading antipodal signals followed by trailing null signals, or leading null signals followed by trailing antipodal signals. The FIR filter look up is configured to exploit these limitations on the input streams yielding a look up table having relatively few entries. Method and apparatus implementations are disclosed.

ROM-based finite impulse response filter for use in mobile telephone

An integrated search processor used in a modem for a spread spectrum communications system buffers receive samples and utilizes a time sliced transform processor operating on successive offsets from the buffer. The search processor autonomously steps through a search as configured by a microprocessor specified search parameter set, which can include the group of antennas to search over, the starting offset and width of the search window to search over, and the number of Walsh symbols to accumulate results at each offset. The search processor calculates the correlation energy at each offset, and presents a summary report of the best paths found in the search to use for demodulation element reassignment. The search is done in a linear fashion independent of the probability that a signal being searched for was transmitted at any given time.

Method of searching for a bursty signal

The present invention involves demodulating a signal in a spread spectrum multiple access system employing a pilot on the forward link. The rake receiver separates the signal processing based on the period over which the processing occurs. Symbol rate processing is performed by a single time-shared multiply-accumulate datapath that services multiple finger front ends and a searcher front end. The front ends are dedicated circuits that perform all chip rate processing, producing a data vector and asserting a flag indicating the results are ready to be serviced by the shared datapath. A datapath controller arbitrates use of the datapath between the finger front ends, the searcher front end, and combining functions, configuring the datapath to service them on a first-come, first-serve basis. The controller sequences the datapath through a fixed routine as dictated by the signal processing associated with the block being serviced.

Mobile demodulator architecture for a spread spectrum multiple access

A modulator for a spread spectrum telecommunication system not only receives local data and processes it, but also receives input data from one or more other modulators, sums the input data with the local data, and provides the sum as data for a subsequent modulator or as final output for a transmit power amplifier. The modulator includes an input block and an output block and, depending on a control data signal, input data will be summed with the internally generated local data of the modulator before being provided to the output block. The output data can include parity data. The parity data can be used to check for faults such as might be introduced, for example, by a faulty connection or broken hard-wired interconnect. If an error is detected, the summation function of the transmit modulator can be automatically disabled.

Serial linked interconnect for summation of multiple waveforms on a

An integrated demodulation processor used in a modem for a spread spectrum communications system despreads multipath receive signals then uses a time sliced transform processor to process the multiple signals in to a single series of soft decision results. The demodulation processor uses a single transform engine which operates on a time slice basis. The output of the processor engine cascade through a pipeline processor which, on a time slice basis, operates on signals corresponding to each multipath receive signal. The processed results are dual maxima decoded to provide soft decision data.

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San Diego, CA, United States of America

Kenneth David Easton