Lucent Technologies Inc.

Agere Systems Guardian Corp.

Agere Systems Inc.

Kenneth Daniel Fitch

Frederick Harrison Fischer

Jalil Fadavi-Ardekani

Ho Trong Nguyen

Avinash Velingker

Walter G Soto

Scott A Segan

Shaun Patrick Whalen

James Frank Vomero

Sucheta Sudhir Chodnekar

Vladimir Sindalovsky

Laurence Edward Bays

Richard J Niescier

Daisuke Takise

Prabhat K Jain

Sonali Bagchi

An semiconductor device including logic circuitry, a plurality of pins, and an interface unit coupling the logic circuitry to the plurality of pins, wherein the interface unit permits any of the pins to be coupled to any portion of the logic circuitry. The semiconductor device provides a template by which many different types of semiconductor devices, with varied pin assignments, can be manufactured, without the need for changing production masks.

Semiconductor device with variable pin locations

A method and apparatus allowing two independent arbiters which do not directly talk to one another to function on a common system bus, allowing efficient operation of a master controller, and virtually endless capability to add peripherals to the common system bus without problems or major modifications commonly associated with additional arbitration overhead. A master controller sets time slot parameters for an external, subordinate arbiter as often as desired. Based on the time slot parameter information, the subordinate arbiter functions on an electrically separated portion of the common system bus during all times but for a time slot associated with communication of the super arbiter over the entire common system bus. During this time, a tri-state buffer element allows communication between portions of the common system bus. In an adaptive arbitration mode, the subordinate arbiter combines static time slot information assigned in configuration registers together with actual bus requests to generate grant signals to the requesting devices, and reassigns all or portions of time slots which, although assigned to a particular device, are left unused for the relevant system cycle. A historical buffer may be maintained for any or all time slots. Using this historical information, long term statistical information may be generated. Moreover, the master controller may re-tune time slot configurations based on the historical information regarding past recent use of the relevant time slots.

Hierarchical bus arbitration

A memory paging method and apparatus using a memory paging register and a memory paging mask register. The invention has particular application in the partition of memory used by more than one software application program. The bits of the memory paging mask register selectably disable bits of the memory paging register to redefine the length and physical characteristics of pages in memory based on the needs of a software program. As a result, the paged partitions in memory may be of variable length and/or may comprise non-contiguous portions of the memory.

System for flexible memory paging in partitioning memory

Programmable time slot interface bus arbiter

A method and apparatus allowing efficient access control to a common data bus by including an isolation device to separate the common data bus, a priority-based arbiter to control access to the internal portion of the common data bus including a processor or other bus master, and a time slot arbiter to control access to the external portion of the common data bus including multiple bus masters, an external memory interface, etc. The common external memory may be allocated for exclusive or non-exclusive use by the various devices utilizing either portion of the isolated common data bus. External devices accessing the external memory may communicate directly with one or more bus masters, e.g., on the internal portion of the common data bus.

Shared devices and memory using split bus and time slot interface bus arbitration

An instruction clock of a processing unit in a low power mode in accordance with the principles of the present invention is qualified with a burst mode control signal. The burst mode control signal is allowed to start and stop the instruction flow of the relevant processing unit. In the disclosed embodiment, a master clock signal is qualified by a clock control circuit to provide bursts of an instruction clock signal to the relevant processing unit. To operate the burst instruction cycle control unit, a user pre-programs a burst length, into a register to set the length of the burst of instruction cycles to the relevant processing unit. A maximum counter value in a counter sets the period of the instruction cycle bursts provided to the relevant processing unit. As long as the current value of the counter is less than or equal to the pre-programmed burst length, the burst control signal allows a clock controller to pass a master clock signal or other relevant clock signal as an instruction clock signal to the relevant processing unit. The low power burst mode and thus the power savings is adjustable according to the combined values of burst length and maximum counter value.

Processor powerdown operation using intermittent bursts of instruction clock

A method of automatically detecting the baud rate of an input signal and an apparatus using the method. A counter is started upon detecting a first transition of the input signal. The counter is stopped upon detecting a second transition of the input signal. After the counter is stopped, the measured count in the counter represents the duration between the first and second transitions of the input signal. The measured count is compared to a plurality of expected counts to determine which of the plurality of expected counts has a value closest to the measured count. The input signal is sampled using a baud rate based on the expected count having a value closest to the measured count.

Method of automatically detecting the baud rate of an input signal and

A resource port that provides a host processor the facility to request, share and access the resources of data communication equipment (DCE), including the memory and I/O registers of the DCE controller. In one embodiment the resource port has a controller request line to provide the host with a facility to request access to the controller resources, and an interface circuit to provide the facility to index all the resources of the DCE. The interface circuit compensates for any disparity between the widths of the controller address bus and the host processor address bus, and between the widths of the host processor data bus and the controller data bus.

Computer bus resource port

An integrated circuit counter is capable of implementing a relatively high count while being testable using a relatively low number of clock cycles. A linear-feedback shift register (LFSR) having n bit positions is used as the counter. The feedback path of the shift register includes an exclusive OR (XOR) gate that couples selected bits back to the input of the register, in order to implement a 2.sup.n -1 counter. Combinatorial logic circuitry is included to test the counter in significantly less than 2.sup.n -1 clock cycles. This allows for implementing a testable 'watchdog timer' that may be used to detect software runaway conditions in microprocessor systems, among other uses.

Testable high count counter

A technique is provided for setting an error status bit in a first-in, first-out memory having data words with associated error bits. When a word having an associated error bit that is set to indicate an error is written into the FIFO, the write pointer is captured, and a flag is set, indicating that the FIFO has a word with an error. If a second word is written which has an error, that pointer value is captured, overwriting the current value. As the FIFO is read, the read pointers are compared with the captured write pointer. When the values are equal, and the FIFO is read, the flag is cleared, indicating that there are no more errors in the FIFO. In an exemplary case, each word in the FIFO has 8 data bits and 3 error bits. A FIFO used in implementing a UART in a modem typically includes 16 or 32 words.

Growing community of inventors

Allentown, PA, United States of America

Kenneth Daniel Fitch