International Business Machines Corporation

S3 Incorporated, Inc.

Kenneth D Wagner

Bernd K Koenemann

Mehran Amerian

Robert Walter Berry, Jr

Philip George Shephard, Iii

William J Scarpero, Jr

Gulsun Yasar

John A Waicukauski

Srinivasan R Iyengar

Theresa L Meyer

James S Allen

An improved scan flip-flop and method of using same. The scan flip-flop has a separate dedicated scan output driven by a scan output signal driver. Scan shift race conditions are minimized by providing a weak scan output signal driver and inserting delay elements within a cell for a scan flip-flop in the scan signal path. The use of the improved scan flip-flop allows for a one-pass scan synthesis process which provides accurate flip-flop cell timing and area information during the design process.

Edge-triggered scan flip-flop and one-pass scan synthesis methodology

An improved routing system and method allow routing of pluralities of signals to circuit blocks on integrated circuit chips using minimal die area. The improved routing system employs a plurality of tri-state buffers, a plurality of conductive lines, and a controller. The circuit block can be driven from remote locations via the tri-state buffers and conductive lines. The tri-state buffers are selectively enabled one at a time by the controller to prevent signal contention. The multiplexors encountered in conventional routing systems are not needed. The improved routing system and method are ideal for routing to and from large circuit blocks which have numerous terminals, such as embedded dynamic random access memory units, embedded static random access memory units, central processing units, arithmetic logic units, register files, and cores generally. The improved routing system and method also allow testing of large circuit blocks with test vectors supplied by built in self test units and or off-chip test equipment.

Efficient routing from multiple sources to embedded DRAM and other large circuit blocks

An integrated circuit includes a first circuit module for generating a plurality of digital signals and a second circuit module for receiving the digital signals. A multiple input signature module receives the digital signals that are received by the second circuit module. The signature module generates and stores a signature value which is indicative of data values of the digital signals over a plurality of cycles. The signature module operates in response to control circuitry, which is responsive to a test signal, to cause the values indicative of the digital signals to be stored to the multiple input signature module, each time that valid signal values are received by the second circuit module. The multiple input signature module may be used for diagnostics by capturing data at a single, predetermined cycle. The module may be initialized to a predetermined value to ensure the signature value or, the single value captured, accurately reflects the data value of the digital signals. The control circuitry is further responsive to a signature data signal for causing data stored in the multiple input signature module to be provided on at least a first output pin of the integrated circuit. The integrated circuit includes scan circuitry and the signature data signal causes the multiple input signature module to form a portion of the scan circuitry.

Multiple input signature testing & diagnosis for embedded blocks in

A method of accurately simulating how design defects and faults are detected in the board design and manufacturing test environments is provided which uses statements in the simulation control language of a fault simulator. The simulation of the operation of electronic boards (which may not yet have been built) in their expected test environments is possible. The set of statements used in the simulation language allows the proposed functional self-test code, also called diagnostic code or power-on self-test code, which is to be executed by a (micro-)processor, to be tested for its effectiveness. The simulation must synchronize the simulated execution of the processor code to be evaluated with the fault detection by the code being evaluated, simulate the use of any attached tester, such as a logic analyzer, and provide data that can be used for programming devices in the test environment. The PROBE statements in the simulation language determine when the simulator starts and ends a measurement window during which faults can be detected by the simulator. These statements can be used to simulate the amount of time a net must remain stable for test equipment to capture its value.

Fault simulation of testing for board circuit failures

A hybrid random pattern self-test approach is employed in an on-chip fashion to provide desired test signals to circuits on the chip. A simplified weighting circuit is shown to be effective even when only a single bit from a linear feedback shift register is employed for random signal generation. The reduction in linear feedback shift register size and associated weighting circuitry enables the apparatus to be much more readily usable in an on-product configuration thus resulting in significant initial and subsequent test circuit advantages.

Hybrid pattern self-testing of integrated circuits

A memory embedded in a integrated processor chip is dynamically stressed tested by repeatedly writing a test pattern to the data locations of the memory in which a high percentage of the memory cells are sequentially written with complementary data in order to create a high stress on the memory devices. The test pattern is generated as a function of the number of address locations of the memory and the number of data bits of a memory data word. The test pattern is rotated each time the memory is addressed. The test pattern preferably has a contiguous group of digits with the number of digits in the contiguous group being a function of the number of address locations and the number of data bits in the memory word. The memory data input register is configured as a recirculating loop and additional dummy bits are added to provide recirculating loops longer than the data input register. A plurality of independent circulating loops may be created in the data input register or in combination with a number of dummy register bits.

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Sunnyvale, CA, United States of America

Kenneth D Wagner