Vlsi Technology, Inc.

Kenneth D Van Egmond

James Allely Rowson

Robert D Shur

Mark R Hartoog

An integrated circuit includes parity chains which serve as test logic. Each parity chain has a series of XOR gates, where one input to each succeeding XOR gate in a chain is tied to the output of the preceding XOR gate. The remaining inputs are tied to nodes of the main logic, thus defining test points. An error at any one of the test points is reflected in the output of the parity chain. The outputs of the parity chains are arranged as parallel inputs to a linear feedback shift register which provides a serial signature which can be analyzed to detect integrated circuit defects.

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Tempe, AZ, United States of America

Kenneth D Van Egmond