Hewlett-packard Company

Other

Coherent, Inc.

Agilent Technologies, Inc.

Kenneth D Scholz

Jacques Leibovitz

Clinton C Chao

Maria L Cobarruviaz

Rajendra D Pendse

David Schleuning

Farid Matta

Kevin C Douglas

Brahram Afshari

Julie Elizabeth Fouquet

John Julian Uebbing

Stephan Hengstler

Albert W Kovalick

V K Nagesh

Cheng-Cheng Chang

Susan J Swindlehurst

Park-Kee Yu

Tyler Sims

Ya Yun Zhu

A diode-laser having an elongated diode-laser emitter is mounted on a relatively massive heat-sink. Two parallel grooves are machined into the heat-sink to leave a relatively narrow elongated ridge of the heat-sink between the grooves. The ridge has a width about equal to or narrower that the width of the emitter. The diode-laser is mounted on the heat-sink such that thermal communication between the emitter and heat-sink is essentially limited to thermal communication with the ridge.

Broad-area edge-emitting semiconductor laser with limited thermal contact

The optical switch operates in two stages. In the first stage, the bubble is &ldquo;blown&rdquo; into the trench. In the second stage, the sidewalls are heated to achieve a dry wall condition by improving the thermal transfer path from the heat source to the reflecting wall. Seperate side heaters are placed in thermal contact to the sidewalls. This results in a switch that is more stable, energy efficient, and has a longer mean time to failure.

Stable optical switch with reduced power consumption

An integrated circuit redistribution structure. The integrated circuit redistribution structure includes a plurality of conductive pads located on an active side of an integrated circuit. The integrated circuit redistribution structure includes a redistribution layer and an under bump material structure for receiving a solder bump. The redistribution layer can include a first mechanically protective layer which adheres to the active side of the integrated circuit. The redistribution layer includes a plurality of conductive lines in which at least one of the conductive lines is connected to at least one conductive pad. Each conductive line includes an adhesion and diffusion barrier layer, an electrical conductor layer, and a first metallic protective layer. The under bump material structure is formed over at least one conductive line. The under bump material structure includes a solder wettable metal layer formed over the redistribution layer, and a second metallic protective layer for receiving the solder bump.

Redistribution layer and under bump material structure for converting

A method for fabricating layers permits the accurate removal of surface material in a multi-layer multi-chip carrier. An intermediate layer of solid vias is deposited over a circuit layer attached to a substrate. The layer can be filled with a dielectric material. The substrate is attached to a substrate holder such that the intermediate layer is exposed, and the substrate holder is placed onto a rotating platen polisher with the intermediate layer facing the platen surface. Tooling presses the intermediate layer against the rotating polishing platen, allowing the substrate holder and substrate to rotate with three degrees of angular freedom, letting the substrate and intermediate layer self-align to the polishing platen in order to uniformly remove material from the intermediate layer surface. A second circuit layer can be formed on the resulting structure. The foregoing steps can be iterated to build a multi-layer structure of circuit layers separated by uniformly thick dielectric and via layers. As an alternative method, substrate attached to a substrate holder is placed against the platen surface of a shaking polisher, allowing the substrate and substrate holder to self-align to the polishing platen. In a third embodiment, where metal irregularities exist along the intermediate layer surface, wiping the surface evenly with cloth soaked in an appropriate etchant can uniformly remove the unwanted metal irregularities.

Multi-layer fabrication in integrated circuit systems

A electrically interconnected assembly includes an electronic component, such as an integrated circuit chip, having a first pattern of contact sites and includes a substrate having a second pattern of contact sites corresponding to the first pattern. The electronic component is demountably connected to the substrate by a bump-and-socket arrangement at each pair of contact sites. One of the contact sites has a raised bump that is received within a depressed area of the other contact site. The raised bumps are pressed into the depressed areas, forming a ring of contact to electrically and mechanically connect the electronic component to the substrate. Preferably, the depressed areas are formed in a compliant material that allows some deformation but not so much as to allow the raised bumps to bottom out against the depressed areas. The assembly may be used in forming multi-chip modules having demountable integrated circuit chips.

Compressive bump-and-socket interconnection scheme for integrated

The invention is embodied in a TAB frame with wide spaced area array contacts. The area array contacts serve to transform the narrow pitch contacts which connect to a chip mounted on the tab frame into wide spaced TAB edge contacts. These area array contacts allow for the convenient connection of the TAB frame to a printed circuit board and eliminate the need for fine line printed circuit board technology to support the TAB assembly.

Tab frame with area array edge contacts

A method for fabricating high density multi-chip carriers for integrated circuits includes the steps of forming a circuit pattern on a substrate, depositing a composite metal layer and a photoresist layer over the circuit pattern, forming apertures in the photoresist layer, forming solid metal vias in the apertures and, then, removing the photoresist layer. After removal of the first photoresist layer, a second photoresist layer is deposited over the solid vias and the circuit pattern. With the second photoresist layer in place, unprotected portions of the composite layer are etched away. Then, the second photoresist layer is stripped away. Next, a layer of photosensitive dielectric material is formed over the structure and, finally, sufficient portions of the photosensitive dielectric material are removed to expose the top surfaces of the solid vias.

Methods for forming high density multi-chip carriers

The invention is embodied in a demountable TAB assembly. By using two springs in series, the present invention is able to maintain reliable contact between the TAB frame and the printed circuit board even if the elastomeric spring relaxes. The present invention also incorporates a novel TAB frame using contacts formed into an area-array. This area-array concept eliminated the need for fine line printed circuit board technology to support the TAB assembly.

Integrated circuit demountable TAB apparatus

A method of forming solid copper vias in a dielectric layer permits stacked vias in a multi-chip carrier. A dielectric layer is deposited over a substrate and lines of a first interconnect layer formed on the substrate. An aperture formed in the dielectric layer is filled with copper by deposition to form a hollow via. Using a photoresist mask, the hollow via is filled solid by electroplating a second amount of copper. The photoresist is then stripped and excess copper extending from the via is polished flat. A second interconnect layer can be formed on the resulting structure. The foregoing steps can be iterated to build a multi-layer structure with stacked vias.

Stacked solid via formation in integrated circuit systems

An interconnection system and method for linking electronic devices such as semiconductor chips. Inner leads of a tape automated bonding frame are aligned with pads on the semiconductor chip. Inner lead bonding fixes the lead frame to the chip. Outer leads of the tape automated bonding frame are brought into an overlapping relationship with conductive traces on a substrate. Rather than microbonding the outer leads to the traces of the substrate, bond wires are attached to the outer leads and the traces, thereby allowing electrical communication of input and output signals therebetween. In one embodiment, the tensile strength of the bond wires is greater than that of the outer leads. In a second embodiment, the bond strength of the wire to the outer lead is greater than the bond strength of the wire to the substrate trace.

Tape automated bonding system which facilitate repair

A method of forming solid copper vias in a dielectric layer permits stacked up vias in a multi-layer multi-chip carrier. An conducting layer is deposited over a substrate and lines of a first interconnect layer formed on the substrate. An aperture formed in a photoresist layer over said lines is filled with copper by electroplating to form a solid via. The via can be polished until its top is flat. Using a photoresist mask, the conductive layer used for electroplating is removed between the lines. A dielectric layer is then formed over the lines and via. A bulge in the dielectric over the via is removed by etching through an aperture defined in a photoresist layer, which is then stripped. A second interconnect layer can be formed on the resulting structure. The foregoing steps can be iterated to build a multi-layer structure with stacked up vias.

Utilizing the method and circuit described herein regulated power is provided by controlling the duty cycle of p. fixed frequency signal as a function of the amplitude of unregulated D.C. voltage applied. A thin film thermal printer utilizing this power regulator is also described herein.

Growing community of inventors

Palo Alto, CA, United States of America

Kenneth D Scholz