Agilent Technologies, Inc.

Keysight Technologies, Inc.

Hewlett-Packard Company

Kenneth D Poulton

Robert M R Neff

Thomas Edward Kopley

Ken A Nishimura

Andrew David Fernandez

Joseph Michael Gorin

Matthew S Holcomb

George Stennis Moore

Mehrdad Heshami

Jorge Pernillo

Vamsi K Srikantam

Stephen T Sparks

Robert E Jewett

Nico Lugil

John J Corcoran

Charles Wu

James Kang

An analog delay line includes a clock generator, an analog sampling circuit, a bank of analog memory cells, a memory controller, an analog readout circuit, and an analog multiplexer. The clock generator is configured to output plural reception clock signals of different frequencies and plural transmission clock signals of different frequencies, the transmission clock signals offset in accumulated phase relative to the reception clock signals. The analog sampling circuit is controlled by at least one of the reception clock signals, and is configured to output a sequence of sampled voltages of an analog input signal. The memory controller is configured to control a write operation at a write frequency of at least one of the reception clock signals and a read operation at a read frequency of at least one of the transmission clock signals. The write operation is for sequentially storing the sampled voltages received from the analog sampling circuit in the bank of analog memory cells, and the read operation is for sequentially reading the sampled voltages from the bank of analog memory cells. The analog readout circuit is configured to buffer the sampled voltages read from the bank of analog memory cells. The analog multiplexer is controlled by at least one of the transmission clock signals, and is configured to multiplex the sampled voltages buffered by the readout circuit to generate an analog output signal. A sampling rate of the analog input signal is within a factor of 2 of a sampling rate of the analog output signal.

Analog delay lines and analog readout systems

A circuit for digital-to-analog conversion includes a first digital-to-analog converter (DAC), a second DAC, and an output node. The first DAC provides charges from multiple first charge sources segmented into a first group for most significant bits of a digital input to the first DAC and a second group for least significant bits of the digital input. Dither is both added to the digital input to the first DAC and used as sole digital input to the second DAC. Analog output from the second DAC is subtracted from analog output of the first DAC at the output node so as to cancel the dither added to the first DAC.

Least significant bit dynamic element matching in a digital-to-analog converter

In an analog-to-digital converter, an analog-to-digital conversion stage comprising a comparator and an analog residual signal generator. The comparator is operable to compare an analog input signal or a sample of the analog input signal with a threshold to generate a bit signal. The analog residual signal generator is operable to generate an analog residual signal from signals comprising the sample of the analog input signal and the bit signal such that, at a level of the analog input signal equal to the threshold of the comparator, the analog residual signal has a level independent of the state of the bit signal. The analog residual signal generator comprises a summing element, a selective inverter and an amplifier in series. The summing element is operable to sum a signal input to it with a reference signal. The selective inverter precedes the summing element, and is operable in response to a first state of the bit signal to pass a signal input to it, and is operable in response to a second state of the bit signal to invert the signal input to it.

Analog-to-digital converter with reduced metastable errors

A digital-to-analog conversion system comprises a digital input, a digital-to-analog converter and a modified digital signal generator. The digital-to-analog converter has a conversion frequency and is subject to a periodic error having a periodicity equal to that of an N-th sub-harmonic of the conversion frequency, where N is an integer. The digital input is operable to receive a digital input signal. The modified digital signal generator is interposed between the digital input and the digital-to-analog converter and is operable in response to the digital input signal to generate a modified digital signal. The modified digital signal comprises a dynamic digital mitigation component that mitigates the periodic error of the digital-to-analog converter.

Sub-harmonic image mitigation in digital-to-analog conversion systems

Staggered interleaved Nyquist regions associated with differing ADC clock rates (F) avoids spectrum lost through disjoint guard bands at the end of or between adjacent Nyquist regions. The staggered interleaved Nyquist regions overlap by an amount at least as much as is consumed by the guard bands. Selectable anti-aliasing filters associated with each Nyquist region and its ADC clock rate are used to enforce the staggered Nyquist regions and their various guard bands. For example, and neglecting guard bands, an initial raw band of operation RBmay be the First Nyquist region for a basic sampling frequency F. An adjacent raw band of operation RBthat overlaps RBmay be the Second Nyquist region for an alternate sampling frequency 2F/3. An adjacent raw band of operation RBthat overlaps RBmay be the Second Nyquist region for the basic sampling frequency F. These raw bands interleave and overlap: In this example the smallest overlap is F/6. We then select widths for guard bands that do not exceed F/6. Additional ADC clock rates and anti-aliasing filters may be used to operate in still higher Nyquist regions.

Staggered interleaved Nyquist regions avoid guard band induced holes when sampling a band limited signal

Staggered consecutive Nyquist regions associated with differing DAC synthesizer clock rates (F) avoids spectrum lost through disjoint guard bands at the end of or between adjacent Nyquist regions. The staggered consecutive Nyquist regions overlap by an amount at least as much as is consumed by the guard bands. Selectable reconstruction filters associated with each Nyquist region and its DAC clock rate are used to enforce the staggered Nyquist regions and their various guard bands.

Discrete synthesis using staggered Nyquist regions avoids guard band induced holes near a Nyquist limit

The present method reduces variations in noise and temperature in a mixed-signal circuit including memory. Memory electrically proximate an analog circuit is provided and a digital data word received at the memory. When the data word is not a desired data word, a dummy write to the memory is performed. When the data word is a desired data word, the data word is written to the memory. The mixed-signal circuit includes an analog circuit, memory electrically proximate to the analog circuit and connected to receive digital data words, and a memory controller connected to the memory. The memory controller is operable to cause the memory to write to the memory each of the data words that is a desired data word and additionally to perform a dummy write to memory for each of the data words that is not a desired data word.

Reduction of noise and temperature variation in mixed-signal integrated circuits

A method for calibrating time interleaved samplers comprising applying a calibration signal to a time-interleaved sampling device, wherein the signal is coherent with at least one sample clock on the device and is periodic and has a predetermined spectral content and frequency, sampling, by said time-interleaved sampling device, the calibration signal at a plurality of phases to form samples, averaging the formed samples, and calculating the phase error of each sample based on the average calibration signal sample.

System and method for timing calibration of time-interleaved data converters

A line driver fabricated from CMOS devices that provides a substantially constant output impedance over a significant range of a time-varying input voltage includes a time-varying current source, a pair of CMOS output loads, and a pair of biasing circuits. Each CMOS output load includes a NMOS transistor and a PMOS transistor connected in parallel and each biased into a linear range of operation. In response to a time-varying input voltage, the time-varying current source draws current from the pair of CMOS output loads in a manner that operates each CMOS output load to collectively establish a time-varying output voltage component at an associated output terminal.

CMOS controlled-impedance transmission line driver

A method of calibrating a high-speed analog to digital converter and an ADC that implements the method. Multiple linear regression analysis is used to calibrate the stages of a pipeline ADC to compensate for variations in gain from stage to stage and optionally to compensate for harmonic distortion. Current amplifiers each having gain of about 1.6 are used for low power consumption, minimal surface area requirements, and rapid sampling speed. Weighting factors are stored in lookup tables to minimize the number of adders required to generate the output digital word.

Method of calibrating an analog-to-digital converter and a circuit implementing the same

The analog-to-digital conversion system comprises an analog-to-digital converter that includes a digital output, memory having a data input and a data output, an output port, an input data bus that extends from the digital output of the analog-to-digital converter to the data input of the memory and an output data bus that extends from the data output of the memory to the output port. The analog-to-digital converter is structured to generate digital samples at a sampling rate. The input data bus is structured to operate at the sampling rate of the ADC. At least one of the data output of the memory, the output data bus and the output port is structured to operate at a maximum rate less than the sampling rate.

Analog-to-digital converter with on-chip memory

Apparatus for introduction of a controllable time delay in the transition of a logic device output signal from a first logical level to a second logical level, in response to change of an input signal, or the difference of two input signals from a third logical level to a fourth logical level, delivered to the logic device. In a first embodiment, a limiting amplifier receives an input signal S.sub.in and a threshold signal V.sub.T at its two terminals and forms an amplified difference output signal S.sub.out. A selected voltage level signal V.sub.L and S.sub.out are received at a signum function module and the output signal sgn(S.sub.out -V.sub.L) is formed and issued. The signum output signal is multiplied by a controllable real number m and is added to V.sub.L to form the threshold signal V.sub.T. The desired output signal S.sub.out makes a transition between the first and second logical levels, with a time delay that is controllable by choice of the number m. In a second embodiment, which also uses a signum function, two input signals, S.sub.in,1 and S.sub.in,2, give rise to two output signals, S.sub.out,1 and S.sub.out,2, and the difference signal S.sub.out,1 -S.sub.out,2 makes a transition between two logical levels with a time delay that depends controllably on choice of the number m.

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Palo Alto, CA, United States of America

Kenneth D Poulton