Xilinx, Inc.

Kenneth D Chapman

Steven P Young

Austin H Lesea

Ching Yee Hu

Jameel Hussein

Methods and systems estimate a rate of corruption of storage bits in a logic circuit. One or more processors execute instructions that cause the processors to perform the operations that follow. A description is input describing an environment of the logic circuit, and the description of the environment includes a position of the logic circuit. An atomic particle flux density at the logic circuit is estimated as a function of the description of the environment. A specification is input that specifies the storage bits in the logic circuit. The rate of corruption of the storage bits is determined as a function of the atomic particle flux density and a quantification of the storage bits in the logic circuit.

Estimating the rate of storage corruption from atomic particles

A correlation circuit arrangement for de-spreading spread spectrum signals. In various embodiments, the correlation circuit arrangement includes an adder-subtractor and a shift register arrangement. The adder-subtractor adds an input sample value to or subtracts the sample value from an accumulated correlation value, responsive to an input PN code. The adder-subtractor is time-multiplexed between one or more PN code generators and correlation values are accumulated in the shift register arrangement. In another embodiment, transmission path delay can be analyzed by using the shift register arrangement to store correlation values that result from delaying the PN code across multiple chip periods.

Method and apparatus for de-spreading spread spectrum signals

An improved CLB architecture, wherein the use of dedicated AND gates to generate a carry chain input signal facilitates low latency multiplication and makes efficient use of four-input function generators. In one embodiment of the invention, when multiplication using a binary addition tree algorithm is used, AND gates to implement single-bit multiplication are provided within the available function generators and duplicated in a dedicated AND gate accessible outside the corresponding function generator as a carry-chain input signal. In another embodiment, carry chain multiplexers can be selectively configured as AND or OR gates to facilitate certain arithmetic or comparison functions for the outputs of a plurality of function generators.

Configurable logic block with and gate for efficient multiplication in FPGAS

Configurable logic block with AND gate for efficient multiplication in FPGAS

A matched filter arrangement and an FPGA-implemented tap arrangement for a matched filter are described in various embodiments. In an n-tap filter to match a code sequence, each of taps,through (n-,) includes a configurable adder-subtractor. A code storage element is coupled to the adder-subtractor to select either addition or subtraction in accordance with a corresponding bit of the code sequence. The output of the adder-subtractor is coupled to a partial-result storage element, which is part of a chain of partial-result storage elements. The last partial-result storage element in the chain is coupled to the data input of an adder-subtractor in another tap. The last tap includes an adder-subtractor and a single storage element for storage of the final result.

Growing community of inventors

Woking, United Kingdom

Kenneth D Chapman