Texas Instruments Corporation

Kenneth D Brennan

Satyavolu Srinivas Papa Rao

David Brian Aldrich

Byron Lovell Williams

Qing-Tang Jiang

Guoqiang Xing

Robert Yung-Hsi Tsu

Darius Lammont Crenshaw

Douglas A Prinslow

Eden M Zielinski

Peter S McAnally

Paul Matthew Gillespie

Stephan Grunow

Mona M Eissa

Robert Kraft

Alwin J Tsao

Hisashi Shichijo

Phillip D Matz

Sameer Kumar Ajmera

Hyesook Hong

William Wesley Dostalik

Steven Alan Lytle

Keith J Brankner

Montray Leavy

Somit Joshi

Yvette Shaw

Yuri E Solomentsev

An inductor structure () formed in an integrated circuit () is disclosed, and includes a first isolation layer () and a first core plate () disposed over or within the first isolation layer (). The first core plate () includes a plurality of electrically coupled conductive traces composed of a conductive ferromagnetic material layer. A second isolation layer () overlies the first isolation layer and an inductor coil () composed of a conductive material layer () is formed within the second isolation layer (). Another core plate may be formed over the coil. The one or more core plates increase an inductance (L) of the inductor coil ().

Method to improve inductance with a high-permeability slotted plate core in an integrated circuit

An integrated circuit capacitor having a bottom plate, a dielectric layer', and a ferromagnetic top plate.

Ferromagnetic capacitor

A method () of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A sidewall spacer () is formed against an edge () of a layer of bottom electrode/copper diffusion barrier material (), an edge () of a layer of capacitor dielectric material () and at least some of an edge () of a layer of top electrode material. The sidewall spacer () is dielectric or non-conductive and mitigates 'shorting' currents that can develop between the plates as a result of copper diffusion. Bottom electrode diffusion barrier material () mitigates copper diffusion and/or copper drift, thereby reducing the likelihood of premature device failure.

Metal insulator metal (MIM) capacitor fabrication with sidewall spacers and aluminum cap (ALCAP) top electrode

The formation of a MIM (metal insulator metal) capacitor () and concurrent formation of a resistor () is disclosed. A copper diffusion barrier () is formed over a copper deposition () that serves as a bottom electrode () of the capacitor (). The copper diffusion barrier () mitigates unwanted diffusion of copper from the copper deposition (), and is formed via electro-less deposition such that little to none of the barrier material is deposited at locations other than over a top surface () of the deposition of copper/bottom electrode. Subsequently, layers of dielectric () and conductive () materials are applied to form a dielectric () and top electrode () of the MIM capacitor (), respectively, where the layer of conductive top electrode material () also functions to concurrently develop the resistor () on the same chip as the capacitor ().

Single mask MIM capacitor and resistor with in trench copper drift barrier

A method of manufacturing an integrated circuit on a semiconductor wafer. The method comprising forming a bottom plate of a capacitorand a bottom portion of an induction coil, forming an etch stop layer', forming a ferromagnetic capacitor top plateand a ferromagnetic core, forming a top portion of the induction coilplus viasthat couple the top portion of the induction coilto the bottom portion of the induction coil

Fabrication of a ferromagnetic inductor core and capacitor electrode in a single photo mask step

An inductor integrated in a semiconductor device comprises a first and second lower electrical trace, an upper electrical trace, aligned at a first end with a first end of the first lower electrical trace and at a second end with a second end of the second lower electrical trace, a first via intercoupling the first end of the upper electrical trace with the first end of the first lower electrical trace, and a second via intercoupling the second end of the upper electrical trace with the second end of the second lower electrical trace.

System for integrating a toroidal inductor in a semiconductor device

An embodiment of the invention is a dual damascene layerof an integrated circuitcontaining a dual damascene pattern liner. Another embodiment of the invention is a method of manufacturing dual damascene layerwhere a dual damascene pattern lineris formed over a cap layerand within via holes. Yet another embodiment of the invention is a method of manufacturing dual damascene layerwhere a dual damascene pattern lineris formed over a cap layerand within trench spaces.

Dual damascene pattern liner

The structure and the fabrication method of an integrated circuit in the horizontal surface of a semiconductor body comprising a dielectric layer over said semiconductor body and a substantially vertical hole through the dielectric layer, the hole having sidewalls and a bottom. A barrier layer is positioned over the dielectric layer including the sidewalls within the hole and the bottom of the hole; the barrier layer is operable to seal copper. A copper-doped transition layer is positioned over the barrier layer; the transition layer has a resistivity higher than pure copper and is operable to strongly bond to copper and to the barrier layer, whereby electomigration reliability is improved. The remainder of said hole is filled with copper. The hole can be either a trench or a trench and a via.

Copper transition layer for improving copper interconnection reliability

Methods are disclosed for forming vias, trenches, and interconnects through diffusion barrier, etch-stop, and dielectric materials for interconnection of electrical devices in dual damascene structures of a semiconductor device. A buried via mask at the etch-stop level provides openings with two or more adjacent via misalignment error regions merged into rectangular windows aligned orthogonal to a long axis of the underlying conductive features of a first metal level. The rectangular windows used together with openings in a hard mask form via portions, and the openings in the hard mask provide trench portions. Via and trench portions coincide during trench or via etch, as well as during hard mask or etch-stop layer etch together forming an interconnect cavity, which may then be filled with a conductive material to provide a conductive interconnect between the conductive feature of the first metal level and a second metal level.

Self aligned vias in dual damascene interconnect, buried mask approach

A shielded planar capacitor structure () is discussed, formed within a Faraday cage () in an integrated circuit device (). The capacitor structure () reduces parasitic capacitances within the integrated circuit device (). The capacitor () comprises a capacitor stack () formed between a first and second metal layers () of the integrated circuit. The capacitor stack () has a first conductive layer formed from a third metal layer () disposed between the first and second metal layers () of the integrated circuit, a dielectric isolation layer () disposed upon the first conductive layer (); and a second conductive layer () disposed upon the dielectric isolation layer () and overlying the first conductive layer (). The structure () further has a first and second isolation layers () disposed upon opposite sides of the capacitor stack (). The Faraday cage () is formed between the first and second metal layers () of the integrated circuit (), comprising a first and second shield layers () each having a plurality of mutually electrically conductive spaced apart traces (). The first and second isolation layers () and the capacitor stack () are sandwiched between the first and second shield layers (). Conductive elements () are distributed around the periphery of the capacitor stack () and the first and second isolation layers (). The conductive traces () of the first shield layer () are connected to the conductive traces () of the second shield layer () through the conductive elements ().

Shielded planar capacitor

A method of forming a via in an integrated circuit is provided. The method includes forming a stack including a first layer, a hard mask layer, and at least one intermediate layer disposed between the first layer and the hard mask layer. The first layer comprises a first metal line. The method further includes forming a channel in the hard mask layer. The channel has a first side and a second side opposite the first side. The method further includes forming a resist layer having an opening extending over both the first and second sides of the channel. The method further includes forming a metal line trench and a via opening aligned with the first and second sides of the channel. The method further includes filling the filling the metal line trench and the via opening with a conductive material to create a second metal line and a via connecting the second metal line with the first metal line.

Self-aligned vias in an integrated circuit structure

An aluminum hardmask ( ) is used for etching a dielectric layer ( ). A fluorine-based etch is used that does not etch the aluminum hardmask ( ). The aluminum hardmask ( ) is then removed by CMP.

Aluminum hardmask for dielectric etch

Treating a low-k dielectric layer ( ) using a highly oxidizing wet solution (e.g., H SO ) to improve patterning. Resist poisoning occurs due to an interaction between low-k films ( ), such as OSG, and DUV resist ( ). The wet treatment is performed to either pre-treat a low-k dielectric ( ) before forming the pattern ( ) or during a rework of the pattern ( ) to reduce resist poisoning.

Growing community of inventors

Austin, TX, United States of America

Kenneth D Brennan